mb/google/poppy: Rework OV5670 power on sequence

In particular:

- Enable regulators *after* configuring the voltage

- Allow 1 ms for the voltages to settle

- Enable clock after powering on regulators

- Remove extra delays between enabling things. The sensor requires 8192
  clock cycles after the reset is lifted before I²C access, so 1 ms is
  enough.

- Make the delay after lifting xshutdown 10 ms. This guarantees that
  streaming will only start once the sensor has had enough time to settle
  after lifting the reset.

BUG=chromium:959232

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sakari Ailus 2019-11-01 12:16:03 +02:00 committed by Patrick Georgi
parent ecfb4b81ae
commit c0b9c8cbc0
1 changed files with 22 additions and 13 deletions

View File

@ -526,30 +526,39 @@ Scope (\_SB.PCI0.I2C2)
daisy chain */ daisy chain */
DOVD(1) DOVD(1)
VAX2 = 1 /* Enable VAUX2 */
if (LNotEqual (AX2V, 52)) { if (LNotEqual (AX2V, 52)) {
/* Set VAUX2 as /* Set VAUX2 as
1.8006 V */ 1.8006 V */
AX2V = 52 AX2V = 52
} }
VAX2 = 1 /* Enable VAUX2 */
\_SB.PCI0.I2C2.PMIC.CGP4(1)
/*
* Wait for DOVDD and AVDD
* to settle.
*/
Sleep(1)
if (LNotEqual (AX1V, 19)) {
/* Set VAUX1 as 1.2132V */
AX1V = 19
}
VAX1 = 1 /* Enable VAUX1 */
/* Wait for VDD to settle. */
Sleep(1) Sleep(1)
\_SB.PCI0.I2C2.PMIC.CLKE() \_SB.PCI0.I2C2.PMIC.CLKE()
CLE1 = 1 CLE1 = 1
VAX1 = 1 /* Enable VAUX1 */
if (LNotEqual (AX1V, 19)) {
/* Set VAUX1 as 1.2132V */
AX1V = 19
}
Sleep(3)
\_SB.PCI0.I2C2.PMIC.CGP4(1)
Sleep(3)
\_SB.PCI0.I2C2.PMIC.CGP5(1) \_SB.PCI0.I2C2.PMIC.CGP5(1)
Sleep(3) /*
* Ensure 10 ms between
* power-up and streamon.
*/
Sleep(10)
STA = 1 STA = 1
} }
} }