ec/google/chromeec: Add APIs for USB-C DP ALT mode
Add API to allow AP to send the command to EC to enter DP ALT mode and API to wait for DP HPD event. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system you will find below message in the coreboot log with or without USB-C display connected: 'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -1508,6 +1508,33 @@ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc,
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return 0;
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}
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int google_chromeec_typec_control_enter_dp_mode(int port)
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{
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if (!google_chromeec_check_feature(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY))
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return 0;
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struct ec_params_typec_control typec_control = {
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.port = port,
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.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
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.mode_to_enter = TYPEC_MODE_DP,
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};
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struct chromeec_command cmd = {
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.cmd_code = EC_CMD_TYPEC_CONTROL,
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.cmd_version = 0,
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.cmd_data_in = &typec_control,
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.cmd_size_in = sizeof(typec_control),
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.cmd_data_out = NULL,
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.cmd_size_out = 0,
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.cmd_dev_index = 0,
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};
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if (google_chromeec_command(&cmd) < 0)
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return -1;
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return 0;
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}
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/**
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* Check for the current mux state in EC. Flags representing the mux state found
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* in ec_commands.h
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@ -1632,6 +1659,25 @@ int google_chromeec_wait_for_displayport(long timeout_ms)
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return ret;
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}
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int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms)
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{
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uint8_t mux_flags;
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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do {
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google_chromeec_usb_get_pd_mux_info(port, &mux_flags);
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if (stopwatch_expired(&sw)) {
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printk(BIOS_WARNING, "HPD not ready after %ldms. Abort.\n", timeout_ms);
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return -1;
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}
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mdelay(100);
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} while (!(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED));
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printk(BIOS_INFO, "HPD ready after %lu ms\n", stopwatch_duration_msecs(&sw));
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return 0;
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}
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int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd)
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{
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struct chromeec_command cmd = {
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@ -40,6 +40,14 @@ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc,
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* >=1: Bitmask of the ports that DP device is connected
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*/
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int google_chromeec_wait_for_displayport(long timeout_ms);
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/* Poll (up to `timeout_ms` ms) for a Hot-Plug Detect (HPD)
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* event on the specified port.
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* Return: 0 on HPD ready, -1 on timeout */
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int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms);
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/* Send command to EC to request to enter DisplayPort ALT mode on the
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* specified port.
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* Return: 0 on success, -1 on error */
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int google_chromeec_typec_control_enter_dp_mode(int port);
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/* Device events */
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uint64_t google_chromeec_get_device_enabled_events(void);
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