Good bye, OLPC...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Nils Jacobs <njacobs8@hetnet.nl> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
e0afe735a0
commit
c0bde289c2
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@ -80,8 +80,6 @@ config VENDOR_NOKIA
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bool "Nokia"
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config VENDOR_NVIDIA
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bool "NVIDIA"
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config VENDOR_OLPC
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bool "OLPC"
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config VENDOR_PC_ENGINES
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bool "PC Engines"
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config VENDOR_RCA
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@ -153,7 +151,6 @@ source "src/mainboard/nec/Kconfig"
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source "src/mainboard/newisys/Kconfig"
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source "src/mainboard/nokia/Kconfig"
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source "src/mainboard/nvidia/Kconfig"
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source "src/mainboard/olpc/Kconfig"
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source "src/mainboard/pcengines/Kconfig"
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source "src/mainboard/rca/Kconfig"
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source "src/mainboard/roda/Kconfig"
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@ -1,20 +0,0 @@
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if VENDOR_OLPC
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choice
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prompt "Mainboard model"
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config BOARD_OLPC_BTEST
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bool "btest"
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config BOARD_OLPC_REV_A
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bool "rev_a"
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endchoice
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source "src/mainboard/olpc/btest/Kconfig"
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source "src/mainboard/olpc/rev_a/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "OLPC"
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endif # VENDOR_OLPC
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@ -1,26 +0,0 @@
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if BOARD_OLPC_BTEST
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_GX2
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select NORTHBRIDGE_AMD_GX2
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select SOUTHBRIDGE_AMD_CS5536
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select UDELAY_TSC
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select CACHE_AS_RAM
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select HAVE_PIRQ_TABLE
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select BOARD_ROMSIZE_KB_256
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config MAINBOARD_DIR
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string
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default olpc/btest
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config MAINBOARD_PART_NUMBER
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string
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default "btest"
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config IRQ_SLOT_COUNT
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int
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default 2
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endif # BOARD_OLPC_BTEST
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@ -1 +0,0 @@
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ROMCCFLAGS=-mcpu=p2 -O
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@ -1,3 +0,0 @@
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -1,75 +0,0 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 1 e 0 dcon_present
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -1,44 +0,0 @@
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chip northbridge/amd/gx2
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register "irqmap" = "0xaa5b"
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
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# Frame Pulse Width = 4clocks
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# IRQ Data Frames = 17Frames
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# SIRQ Mode = continous , It would be better if the EC could operate in
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# Active(Quiet) mode. Save power....
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# SIRQ Enable = Enabled
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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#register "lpc_irq" = "0x00001002"
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#register "lpc_serirq_enable" = "0xEFFD0080"
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#register "enable_gpio0_inta" = "1"
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#register "enable_ide_nand_flash" = "1"
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#register "enable_uarta" = "1"
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#register "enable_USBP4_host" = "1"
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#register "audio_irq" = "5"
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#register "usbf4_irq" = "10"
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#register "usbf5_irq" = "10"
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#register "usbf6_irq" = "0"
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#register "usbf7_irq" = "0"
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
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register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
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register "unwanted_vpci[2]" = "0" # End of list has a zero
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end
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end
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end
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@ -1,31 +0,0 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
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*
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* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
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0x800, /* IRQs devoted exclusively to PCI usage */
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0x1078, /* Vendor */
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0x2, /* Device */
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0, /* Miniport data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
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{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -1,137 +0,0 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <pc80/mc146818rtc.h>
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#include "chip.h"
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#include "southbridge/amd/cs5536/cs5536_smbus2.h"
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#include <cpu/amd/vr.h>
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/* Borrowed from mc146818rtc.c */
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#define CMOS_READ(addr) ({ \
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outb((addr),RTC_PORT(0)); \
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inb(RTC_PORT(1)); \
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})
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#define CMOS_WRITE(val, addr) ({ \
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outb((addr),RTC_PORT(0)); \
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outb((val),RTC_PORT(1)); \
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})
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static void write_bit(unsigned char val) {
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unsigned char byte = CMOS_READ(440 / 8);
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/* Don't change it if its already set */
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if ((byte & 1) == (val & 1))
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return;
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byte &= ~1;
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byte |= val & 1;
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CMOS_WRITE(val, 440/8);
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}
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static unsigned short _getsmbusbase(void) {
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unsigned devfn = PCI_DEVFN(0xf, 0);
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device_t dev = dev_find_slot(0x0, devfn);
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unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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return (unsigned short) (addr & ~1);
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}
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static void init_dcon(void) {
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int ret = 1;
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unsigned short rev = 0;
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unsigned short iobase = _getsmbusbase();
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printk(BIOS_DEBUG, "CHECKING FOR DCON (%x)\n", iobase);
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/* Get the IO base for the SMBUS */
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rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
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if (rev & 0xDC00) {
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printk(BIOS_DEBUG, "DCON FOUND - REV %x\n", rev);
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/* Enable the DCON */
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ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
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if (ret != 0)
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printk(BIOS_DEBUG, "DCON ENABLE FAILED %d\n", ret);
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}
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else
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printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);
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write_bit(rev > 0 ? 1 : 0);
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}
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static void
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init_cafe_irq(void){
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const unsigned char slots_cafe[4] = {11, 0, 0, 0};
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/* CAFE PCI slots */
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pci_assign_irqs(0, 0x0C, slots_cafe);
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/* Make the pin assignments - NOTENOTENOTE: This should be
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* configurable!
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*/
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/* Configure the GPIO pins to use - class 0, index 9 to configure
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* AB. Write 0xFF to disable
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*/
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vrWrite(0x9, 0XFF00);
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/* Configure the GPIO pins to use - class 0, index A to configure
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* CD. Write 0xFF to disable
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*/
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vrWrite(0xA, 0xFFFF);
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}
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static void init(struct device *dev) {
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/*
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unsigned bus = 0;
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unsigned devfn = PCI_DEVFN(0xf, 4);
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device_t usb = NULL;
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unsigned char usbirq = 0xa;
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*/
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printk(BIOS_DEBUG, "OLPC BTEST ENTER %s\n", __func__);
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#if 0
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/* I can't think of any reason NOT to just set this. If it turns out we want this to be
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* conditional we can make it a config variable later.
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*/
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printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n",
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__func__, bus, devfn, usbirq);
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usb = dev_find_slot(bus, devfn);
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if (! usb){
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printk(BIOS_ERR, "Could not find USB\n");
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} else {
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pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
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}
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#endif
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init_dcon();
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init_cafe_irq();
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printk(BIOS_DEBUG, "OLPC BTEST EXIT %s\n", __func__);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("OLPC btest Mainboard")
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.enable_dev = enable_dev,
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};
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@ -1,182 +0,0 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/hlt.h>
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#include <console/console.h>
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#include "lib/ramtest.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#include <cpu/amd/geode_post_code.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static inline unsigned int fls(unsigned int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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/* sdram parameters for OLPC:
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row address = 13
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col address = 9
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banks = 4
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dimm0size=128MB
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d0_MB=1 (module banks)
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d0_cb=4 (component banks)
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do_psz=4KB (page size)
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Trc=10 (clocks) (ref2act)
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Tras=7 (act2pre)
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Trcd=3 (act2cmd)
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Trp=3 (pre2act)
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Trrd=2 (act2act)
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Tref=17.8ms
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = 1;
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = 4;
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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/* get the module bank density, SPD byte 31 */
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/* this is multiples of 8 MB */
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/* actually it is 2^x*4, where x is the value you put in */
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/* for OLPC, set default size */
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/* dimm size - hardcoded 128Mb */
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val = 5;
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msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
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/* page size = 2^col address */
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val = 2; /* 4096 bytes */
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\n");
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/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
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/* well, it may be close. It's about 200,000 ticks */
|
||||
msr.lo = 0x00003000;
|
||||
wrmsr(MC_CF07_DATA, msr);
|
||||
|
||||
/* timing and mode ... */
|
||||
|
||||
msr = rdmsr(0x20000019);
|
||||
|
||||
/* per standard bios settings */
|
||||
|
||||
msr.hi = 0x18000108;
|
||||
msr.lo =
|
||||
(6<<28) | // cas_lat
|
||||
(10<<24)| // ref2act
|
||||
(7<<20)| // act2pre
|
||||
(3<<16)| // pre2act
|
||||
(3<<12)| // act2cmd
|
||||
(2<<8)| // act2act
|
||||
(2<<6)| // dplwr
|
||||
(2<<4)| // dplrd
|
||||
(3); // dal
|
||||
/* the msr value reported by quanta is very, very different.
|
||||
* we will go with that value for now.
|
||||
*/
|
||||
msr.lo = 0x286332a3;
|
||||
|
||||
wrmsr(0x20000019, msr);
|
||||
|
||||
}
|
||||
|
||||
#include "northbridge/amd/gx2/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
#define PLLMSRhi 0x00001490
|
||||
#define PLLMSRlo 0x02000030
|
||||
#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
|
||||
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
|
||||
#include "northbridge/amd/gx2/pll_reset.c"
|
||||
#include "cpu/amd/model_gx2/cpureginit.c"
|
||||
#include "cpu/amd/model_gx2/syspreinit.c"
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
unsigned long m;
|
||||
|
||||
/* Make sure events enable for gpio 12 is off */
|
||||
|
||||
m = inl(GPIOL_EVENTS_ENABLE);
|
||||
m &= ~GPIOL_12_SET;
|
||||
m |= GPIOL_12_CLEAR;
|
||||
outl(m, GPIOL_EVENTS_ENABLE);
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl [] = {
|
||||
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
|
||||
cs5536_setup_onchipuart(1);
|
||||
gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset();
|
||||
|
||||
cpuRegInit();
|
||||
print_err("done cpuRegInit\n");
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check all of memory */
|
||||
//ram_check(0x00000000, 640*1024);
|
||||
}
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
if BOARD_OLPC_REV_A
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select ARCH_X86
|
||||
select CPU_AMD_GX2
|
||||
select NORTHBRIDGE_AMD_GX2
|
||||
select SOUTHBRIDGE_AMD_CS5536
|
||||
select UDELAY_TSC
|
||||
select CACHE_AS_RAM
|
||||
select HAVE_PIRQ_TABLE
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default olpc/rev_a
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "rev_a"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_OLPC_REV_A
|
||||
|
|
@ -1 +0,0 @@
|
|||
ROMCCFLAGS=-mcpu=p2 -O
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
extern struct chip_operations mainboard_ops;
|
||||
|
||||
struct mainboard_config {};
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 1 e 0 dcon_present
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
chip northbridge/amd/gx2
|
||||
register "irqmap" = "0xaa5b"
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_gx2
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
|
||||
# Frame Pulse Width = 4clocks
|
||||
# IRQ Data Frames = 17Frames
|
||||
# SIRQ Mode = continous , It would be better if the EC could operate in
|
||||
# Active(Quiet) mode. Save power....
|
||||
# SIRQ Enable = Enabled
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
#register "lpc_irq" = "0x00001002"
|
||||
#register "lpc_serirq_enable" = "0xEFFD0080"
|
||||
#register "enable_gpio0_inta" = "1"
|
||||
#register "enable_ide_nand_flash" = "1"
|
||||
#register "enable_uarta" = "1"
|
||||
#register "enable_USBP4_host" = "1"
|
||||
#register "audio_irq" = "5"
|
||||
#register "usbf4_irq" = "10"
|
||||
#register "usbf5_irq" = "10"
|
||||
#register "usbf6_irq" = "0"
|
||||
#register "usbf7_irq" = "0"
|
||||
device pci d.0 on end # Realtek 8139 LAN
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
|
||||
register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
|
||||
register "unwanted_vpci[2]" = "0" # End of list has a zero
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/io.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include "chip.h"
|
||||
#include "southbridge/amd/cs5536/cs5536_smbus2.h"
|
||||
|
||||
/* Borrowed from mc146818rtc.c */
|
||||
|
||||
#define CMOS_READ(addr) ({ \
|
||||
outb((addr),RTC_PORT(0)); \
|
||||
inb(RTC_PORT(1)); \
|
||||
})
|
||||
|
||||
#define CMOS_WRITE(val, addr) ({ \
|
||||
outb((addr),RTC_PORT(0)); \
|
||||
outb((val),RTC_PORT(1)); \
|
||||
})
|
||||
|
||||
static void write_bit(unsigned char val) {
|
||||
|
||||
unsigned char byte = CMOS_READ(440 / 8);
|
||||
|
||||
/* Don't change it if its already set */
|
||||
|
||||
if ((byte & 1) == (val & 1))
|
||||
return;
|
||||
|
||||
byte &= ~1;
|
||||
byte |= val & 1;
|
||||
CMOS_WRITE(val, 440/8);
|
||||
}
|
||||
|
||||
static unsigned short _getsmbusbase(void) {
|
||||
unsigned devfn = PCI_DEVFN(0xf, 0);
|
||||
device_t dev = dev_find_slot(0x0, devfn);
|
||||
unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
|
||||
return (unsigned short) (addr & ~1);
|
||||
}
|
||||
|
||||
static void init_dcon(void) {
|
||||
|
||||
int ret = 1;
|
||||
unsigned short rev = 0;
|
||||
unsigned short iobase = _getsmbusbase();
|
||||
|
||||
printk(BIOS_DEBUG, "CHECKING FOR DCON (%x)\n", iobase);
|
||||
|
||||
/* Get the IO base for the SMBUS */
|
||||
|
||||
rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
|
||||
|
||||
if (rev & 0xDC00) {
|
||||
printk(BIOS_DEBUG, "DCON FOUND - REV %x\n", rev);
|
||||
|
||||
/* Enable the DCON */
|
||||
ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
|
||||
if (ret != 0)
|
||||
printk(BIOS_DEBUG, "DCON ENABLE FAILED %d\n", ret);
|
||||
}
|
||||
else
|
||||
printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);
|
||||
|
||||
write_bit(rev > 0 ? 1 : 0);
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
/*
|
||||
unsigned bus = 0;
|
||||
unsigned devfn = PCI_DEVFN(0xf, 4);
|
||||
device_t usb = NULL;
|
||||
unsigned char usbirq = 0xa;
|
||||
*/
|
||||
|
||||
printk(BIOS_DEBUG, "OLPC REVA ENTER %s\n", __func__);
|
||||
|
||||
#if 0
|
||||
/* I can't think of any reason NOT to just set this. If it turns out we want this to be
|
||||
* conditional we can make it a config variable later.
|
||||
*/
|
||||
|
||||
printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n",
|
||||
__func__, bus, devfn, usbirq);
|
||||
usb = dev_find_slot(bus, devfn);
|
||||
if (! usb){
|
||||
printk(BIOS_ERR, "Could not find USB\n");
|
||||
} else {
|
||||
pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
|
||||
}
|
||||
#endif
|
||||
|
||||
init_dcon();
|
||||
printk(BIOS_DEBUG, "OLPC REVA EXIT %s\n", __func__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("OLPC rev_a Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <console/console.h>
|
||||
#include "lib/ramtest.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "cpu/x86/msr.h"
|
||||
#include <cpu/amd/gx2def.h>
|
||||
#include <cpu/amd/geode_post_code.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/gx2/raminit.h"
|
||||
|
||||
static inline unsigned int fls(unsigned int x)
|
||||
{
|
||||
int r;
|
||||
|
||||
__asm__("bsfl %1,%0\n\t"
|
||||
"jnz 1f\n\t"
|
||||
"movl $32,%0\n"
|
||||
"1:" : "=r" (r) : "g" (x));
|
||||
return r;
|
||||
}
|
||||
|
||||
/* sdram parameters for OLPC:
|
||||
row address = 13
|
||||
col address = 9
|
||||
banks = 4
|
||||
dimm0size=128MB
|
||||
d0_MB=1 (module banks)
|
||||
d0_cb=4 (component banks)
|
||||
do_psz=4KB (page size)
|
||||
Trc=10 (clocks) (ref2act)
|
||||
Tras=7 (act2pre)
|
||||
Trcd=3 (act2cmd)
|
||||
Trp=3 (pre2act)
|
||||
Trrd=2 (act2act)
|
||||
Tref=17.8ms
|
||||
*/
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
|
||||
* component Banks (byte 17) * module banks, side (byte 5) *
|
||||
* width in bits (byte 6,7)
|
||||
* = Density per side (byte 31) * number of sides (byte 5) */
|
||||
/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
|
||||
msr_t msr;
|
||||
unsigned char module_banks, val;
|
||||
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
|
||||
/* get module banks (sides) per dimm, SPD byte 5 */
|
||||
module_banks = 1;
|
||||
module_banks >>= 1;
|
||||
msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
|
||||
msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
|
||||
|
||||
/* get component banks per module bank, SPD byte 17 */
|
||||
val = 4;
|
||||
val >>= 2;
|
||||
msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
|
||||
msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
|
||||
|
||||
/* get the module bank density, SPD byte 31 */
|
||||
/* this is multiples of 8 MB */
|
||||
/* actually it is 2^x*4, where x is the value you put in */
|
||||
/* for OLPC, set default size */
|
||||
/* dimm size - hardcoded 128Mb */
|
||||
val = 5;
|
||||
msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
|
||||
msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
|
||||
|
||||
/* page size = 2^col address */
|
||||
val = 2; /* 4096 bytes */
|
||||
msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
|
||||
msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
|
||||
|
||||
print_debug("computed msr.hi ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug("\n");
|
||||
|
||||
/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
|
||||
/* well, it may be close. It's about 200,000 ticks */
|
||||
msr.lo = 0x00003000;
|
||||
wrmsr(MC_CF07_DATA, msr);
|
||||
|
||||
/* timing and mode ... */
|
||||
|
||||
msr = rdmsr(0x20000019);
|
||||
|
||||
/* per standard bios settings */
|
||||
|
||||
msr.hi = 0x18000108;
|
||||
msr.lo =
|
||||
(6<<28) | // cas_lat
|
||||
(10<<24)| // ref2act
|
||||
(7<<20)| // act2pre
|
||||
(3<<16)| // pre2act
|
||||
(3<<12)| // act2cmd
|
||||
(2<<8)| // act2act
|
||||
(2<<6)| // dplwr
|
||||
(2<<4)| // dplrd
|
||||
(3); // dal
|
||||
/* the msr value reported by quanta is very, very different.
|
||||
* we will go with that value for now.
|
||||
*/
|
||||
msr.lo = 0x286332a3;
|
||||
|
||||
wrmsr(0x20000019, msr);
|
||||
|
||||
}
|
||||
|
||||
#include "northbridge/amd/gx2/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
#define PLLMSRhi 0x00001490
|
||||
#define PLLMSRlo 0x02000030
|
||||
#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
|
||||
#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
|
||||
#include "northbridge/amd/gx2/pll_reset.c"
|
||||
#include "cpu/amd/model_gx2/cpureginit.c"
|
||||
#include "cpu/amd/model_gx2/syspreinit.c"
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
unsigned long m;
|
||||
|
||||
/* Make sure events enable for gpio 12 is off */
|
||||
|
||||
m = inl(GPIOL_EVENTS_ENABLE);
|
||||
m &= ~GPIOL_12_SET;
|
||||
m |= GPIOL_12_CLEAR;
|
||||
outl(m, GPIOL_EVENTS_ENABLE);
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl [] = {
|
||||
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
|
||||
cs5536_setup_onchipuart(1);
|
||||
gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset();
|
||||
|
||||
cpuRegInit();
|
||||
print_err("done cpuRegInit\n");
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check all of memory */
|
||||
//ram_check(0x00000000, 640*1024);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue