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soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers 

Picasso has 32 configurable GPEs, not only 28.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-02 23:48:35 +01:00
parent 404aea866c
commit c0dbd4cb56
1 changed files with 4 additions and 4 deletions
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8
src/soc/amd/picasso/include/soc/southbridge.h
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@ -75,6 +75,10 @@
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)
#define PM_LPC_ENABLE BIT(0) #define PM_LPC_ENABLE BIT(0)
#define PM1_LIMIT 16
#define GPE0_LIMIT 32
#define TOTAL_BITS(a) (8 * sizeof(a))
/* FCH MISC Registers 0xfed80e00 */ /* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00 #define GPP_CLK_CNTRL 0x00
#define GPP_CLK0_REQ_SHIFT 0 #define GPP_CLK0_REQ_SHIFT 0
@ -135,10 +139,6 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
#define TOTAL_BITS(a) (8 * sizeof(a))
/* SATA Controller D11F0 */ /* SATA Controller D11F0 */
#define SATA_MISC_CONTROL_REG 0x40 #define SATA_MISC_CONTROL_REG 0x40
#define SATA_MISC_SUBCLASS_WREN BIT(0) #define SATA_MISC_SUBCLASS_WREN BIT(0)