soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -52,9 +52,6 @@
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#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
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#define PM_ACPI_NB_PME_GEVENT BIT(28)
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#define PM_ACPI_RTC_WAKE_EN BIT(29)
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN BIT(5)
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#define KBRSTEN BIT(4)
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#define PM_LPC_GATING 0xec
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#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
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#define PM_LPC_A20_EN BIT(1)
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@ -26,6 +26,9 @@
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#define LEGACY_DMA_IO_EN (1 << 2)
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#define CF9_IO_EN (1 << 1)
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#define LEGACY_IO_EN (1 << 0)
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN (1 << 5)
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#define KBRSTEN (1 << 4)
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#define PM_RST_STATUS 0xc0
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/*
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@ -68,8 +68,6 @@
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#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
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#define PM_ACPI_NB_PME_GEVENT BIT(28)
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#define PM_ACPI_RTC_WAKE_EN BIT(29)
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN BIT(5)
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#define PM_LPC_GATING 0xec
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#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
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#define PM_LPC_A20_EN BIT(1)
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@ -70,8 +70,6 @@
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#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
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#define PM_ACPI_NB_PME_GEVENT BIT(28)
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#define PM_ACPI_RTC_WAKE_EN BIT(29)
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#define PM_RST_CTRL1 0xbe
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#define SLPTYPE_CONTROL_EN BIT(5)
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#define PM_PCIB_CFG 0xea
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#define PM_GENINT_DISABLE BIT(0)
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#define PM_LPC_GATING 0xec
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