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soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header 

TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Felix Held 2021-03-25 00:50:34 +01:00
parent 51d6f5cc0a
commit c1042ba2c5
4 changed files with 3 additions and 7 deletions
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3
src/soc/amd/cezanne/include/soc/southbridge.h
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@ -52,9 +52,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5)
#define KBRSTEN BIT(4)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)

3
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -26,6 +26,9 @@
#define LEGACY_DMA_IO_EN (1 << 2) #define LEGACY_DMA_IO_EN (1 << 2)
#define CF9_IO_EN (1 << 1) #define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0) #define LEGACY_IO_EN (1 << 0)
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN (1 << 5)
#define KBRSTEN (1 << 4)
#define PM_RST_STATUS 0xc0 #define PM_RST_STATUS 0xc0
/* /*

2
src/soc/amd/picasso/include/soc/southbridge.h
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@ -68,8 +68,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)

2
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -70,8 +70,6 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_PCIB_CFG 0xea #define PM_PCIB_CFG 0xea
#define PM_GENINT_DISABLE BIT(0) #define PM_GENINT_DISABLE BIT(0)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec