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mb/google/brya: Remove I2C4 usage in devicetree.cb 

I2C4 is not used pn Brya hence make below changes:
1. Disable it in SerialIoI2cMode.
2. Remove I2C4 config in common_soc_config.

TEST=Make sure FSP is not programming I2C4.

Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2021-06-03 22:04:00 +05:30
parent 2e665eb8da
commit c11d4fb0b0
1 changed files with 1 additions and 4 deletions
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5
src/mainboard/google/brya/variants/baseboard/devicetree.cb
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@ -68,7 +68,7 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
}" }"
@ -118,9 +118,6 @@ chip soc/intel/alderlake
.early_init = 1, .early_init = 1,
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
}, },
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = { .i2c[5] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
}, },