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soc/intel: Add GPI interrupt config register offset info 

Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.

BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.

Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2019-04-23 15:18:51 -06:00 committed by Patrick Georgi
parent 91ead42f4b
commit c126084bc5
14 changed files with 76 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/apollolake/gpio_apl.c
View File

@ -57,6 +57,8 @@ static const struct pad_community apl_gpio_communities[] = {
.gpi_status_offset = 0,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -74,6 +76,8 @@ static const struct pad_community apl_gpio_communities[] = {
.gpi_status_offset = NUM_SW_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -91,6 +95,8 @@ static const struct pad_community apl_gpio_communities[] = {
.gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -109,6 +115,8 @@ static const struct pad_community apl_gpio_communities[] = {
+ NUM_SW_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

8
src/soc/intel/apollolake/gpio_glk.c
View File

@ -57,6 +57,8 @@ static const struct pad_community glk_gpio_communities[] = {
.gpi_status_offset = 0,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -74,6 +76,8 @@ static const struct pad_community glk_gpio_communities[] = {
.gpi_status_offset = NUM_NW_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -91,6 +95,8 @@ static const struct pad_community glk_gpio_communities[] = {
.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -109,6 +115,8 @@ static const struct pad_community glk_gpio_communities[] = {
NUM_AUDIO_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

1
src/soc/intel/apollolake/include/soc/gpio_apl.h
View File

@ -49,6 +49,7 @@
#define PAD_CFG_BASE 0x500
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x140

1
src/soc/intel/apollolake/include/soc/gpio_glk.h
View File

@ -282,6 +282,7 @@
*/
#define HOSTSW_OWN_REG_0 0xB0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x170

10
src/soc/intel/cannonlake/gpio.c
View File

@ -85,6 +85,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -101,6 +103,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -117,6 +121,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -133,6 +139,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -149,6 +157,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

10
src/soc/intel/cannonlake/gpio_cnp_h.c
View File

@ -87,6 +87,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -103,6 +105,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -119,6 +123,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -135,6 +141,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -151,6 +159,8 @@ static const struct pad_community cnl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

2
src/soc/intel/cannonlake/include/soc/gpio_defs.h
View File

@ -246,6 +246,8 @@
#define GPE_DW_SHIFT 8
#define GPE_DW_MASK 0xfff00
#define HOSTSW_OWN_REG_0 0xb0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600

2
src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
View File

@ -320,6 +320,8 @@
#define GPE_DW_SHIFT 8
#define GPE_DW_MASK 0xfff00
#define HOSTSW_OWN_REG_0 0xc0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600

6
src/soc/intel/common/block/include/intelblocks/gpio.h
View File

@ -105,8 +105,10 @@ struct pad_community {
gpio_t first_pad; /* first pad in community */
gpio_t last_pad; /* last pad in community */
uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */
uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI EN Reg 0 */
uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI STS Reg 0 */
uint16_t gpi_int_sts_reg_0; /* offset to GPI Int STS Reg 0 */
uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */
uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */
uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */
uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */
uint8_t gpi_status_offset; /* specifies offset in struct
gpi_status */

8
src/soc/intel/denverton_ns/gpio.c
View File

@ -58,6 +58,8 @@ static const struct pad_community dnv_gpio_communities[] = {
NUM_SC0_GPI_REGS,
.pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET,
.host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN,
.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS,
.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE,
.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS,
.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -75,6 +77,8 @@ static const struct pad_community dnv_gpio_communities[] = {
.gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS,
.pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET,
.host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN,
.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS,
.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE,
.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS,
.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -92,6 +96,8 @@ static const struct pad_community dnv_gpio_communities[] = {
.gpi_status_offset = NUM_NC_GPI_REGS,
.pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET,
.host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN,
.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS,
.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE,
.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS,
.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -109,6 +115,8 @@ static const struct pad_community dnv_gpio_communities[] = {
.gpi_status_offset = 0,
.pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET,
.host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN,
.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS,
.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE,
.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS,
.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

10
src/soc/intel/icelake/gpio.c
View File

@ -84,6 +84,8 @@ static const struct pad_community icl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -100,6 +102,8 @@ static const struct pad_community icl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -116,6 +120,8 @@ static const struct pad_community icl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -132,6 +138,8 @@ static const struct pad_community icl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -148,6 +156,8 @@ static const struct pad_community icl_communities[] = {
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

2
src/soc/intel/icelake/include/soc/gpio_defs.h
View File

@ -265,6 +265,8 @@
#define GPE_DW_SHIFT 8
#define GPE_DW_MASK 0xfff00
#define HOSTSW_OWN_REG_0 0xb0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600

8
src/soc/intel/skylake/gpio.c
View File

@ -73,6 +73,8 @@ static const struct pad_community skl_gpio_communities[] = {
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -93,6 +95,8 @@ static const struct pad_community skl_gpio_communities[] = {
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -114,6 +118,8 @@ static const struct pad_community skl_gpio_communities[] = {
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@ -130,6 +136,8 @@ static const struct pad_community skl_gpio_communities[] = {
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,

2
src/soc/intel/skylake/include/soc/gpio_defs.h
View File

@ -225,6 +225,8 @@
#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
#define HOSTSW_OWN_REG_0 0xd0
#define PAD_CFG_BASE 0x400
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1a0