mb/google/fizz: Determine PsysPl3 and Pl4 values
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. According to Intel doc #560604, page 74, the max time window is 64ms (code=6) and the min duty cycle we can set is 4%. BUG=b:71594855 BRANCH=None TEST=Boot to OS and check MSRs using iotools for expected values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -39,6 +39,8 @@
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#define FIZZ_PL2_U22 29
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#define FIZZ_PL2_U22 29
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#define FIZZ_PSYSPL2_U22 65
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#define FIZZ_PSYSPL2_U22 65
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#define FIZZ_PSYSPL2_U42 90
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#define FIZZ_PSYSPL2_U42 90
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#define FIZZ_MAX_TIME_WINDOW 6
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#define FIZZ_MIN_DUTYCYCLE 4
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/*
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/*
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* For type-C chargers, set PL2 to 90% of max power to account for
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* For type-C chargers, set PL2 to 90% of max power to account for
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* cable loss and FET Rdson loss in the path from the source.
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* cable loss and FET Rdson loss in the path from the source.
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@ -121,28 +123,32 @@ static uint8_t board_sku_id(void)
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*
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*
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* Set Pl2 and SysPl2 values based on detected charger.
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* Set Pl2 and SysPl2 values based on detected charger.
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* If detected barrel jack, use values below based on SKU.
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* If detected barrel jack, use values below based on SKU.
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* +-------------+-----+---------+-----+------+------+
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* definitions:
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* | sku_id | PL2 | PsysPL2 | PL4 | Pmax | Prop |
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* x = no value entered. Use default value in parenthesis.
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* +-------------+-----+---------+-----+------+------+
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* will set 0 to anything that shouldn't be set.
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* | i7 U42 | 44 | 81 | 71 | 120 | 48 |
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* n = max value of power adapter.
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* | i5 U42 | 44 | 81 | 71 | 120 | 48 |
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* +-------------+-----+---------+-----------+-------+
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* | i3 U42 | 44 | 81 | 71 | 120 | 48 |
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* | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
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* | i7 U22 | 29 | 58 | 43 | 91 | 48 |
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* +-------------+-----+---------+-----------+-------+
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* | i5 U22 | 29 | 58 | 43 | 91 | 48 |
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* | i7 U42 | 44 | 81 | x(.85PL4) | x(71) |
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* | i3 U22 | 29 | 58 | 43 | 91 | 48 |
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* | i5 U42 | 44 | 81 | x(.85PL4) | x(71) |
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* | celeron U22 | 29 | 58 | 43 | 91 | 48 |
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* | i3 U42 | 44 | 81 | x(.85PL4) | x(71) |
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* +-------------+-----+---------+-----+------+------+
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* | i7 U22 | 29 | 58 | x(.85PL4) | x(43) |
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* | i5 U22 | 29 | 58 | x(.85PL4) | x(43) |
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* | i3 U22 | 29 | 58 | x(.85PL4) | x(43) |
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* | celeron U22 | 29 | 58 | x(.85PL4) | x(43) |
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* +-------------+-----+---------+-----------+-------+
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* For USB C charger:
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* For USB C charger:
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* +-------------+-----+---------+-----+------+------+
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* +-------------+-----+---------+---------+-------+
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* | Max Power(W)| PL2 | PsysPL2 | PL4 | Pmax | Prop |
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* | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
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* +-------------+-----+---------+-----+------+------+
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* +-------------+-----+---------+---------+-------+
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* | 60 (U42) | 44 | 54 | 54 | 120 | 48 |
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* | 60 (U42) | 44 | 54 | 54 | 54 |
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* | 60 (U22) | 29 | 54 | 43 | 91 | 48 |
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* | 60 (U22) | 29 | 54 | 54 | x(43) |
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* | X (U42) | 44 | .9X | .9X | 120 | 48 |
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* | n (U42) | 44 | .9n | .9n | .9n |
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* | X (U22) | 29 | .9X | .9X | 91 | 48 |
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* | n (U22) | 29 | .9n | .9n | x(43) |
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* +-------------+-----+---------+-----+------+------+
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* +-------------+-----+---------+---------+-------+
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*/
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*/
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static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val)
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static void mainboard_set_power_limits(config_t *conf)
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{
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{
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enum usb_chg_type type;
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enum usb_chg_type type;
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u32 watts;
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u32 watts;
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@ -157,6 +163,7 @@ static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val)
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pl2 = FIZZ_PL2_U22;
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pl2 = FIZZ_PL2_U22;
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if ((1 << sku) & u42_mask)
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if ((1 << sku) & u42_mask)
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pl2 = FIZZ_PL2_U42;
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pl2 = FIZZ_PL2_U42;
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conf->tdp_psyspl3 = conf->tdp_pl4 = 0;
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/* If we can't get charger info or not PD charger, assume barrel jack */
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/* If we can't get charger info or not PD charger, assume barrel jack */
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if (rv != 0 || type != USB_CHG_TYPE_PD) {
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if (rv != 0 || type != USB_CHG_TYPE_PD) {
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@ -166,13 +173,20 @@ static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val)
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if ((1 << sku) & u42_mask)
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if ((1 << sku) & u42_mask)
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psyspl2 = FIZZ_PSYSPL2_U42;
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psyspl2 = FIZZ_PSYSPL2_U42;
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} else {
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} else {
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/* Base on max value of adapter */
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/* Detected TypeC. Base on max value of adapter */
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psyspl2 = watts;
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psyspl2 = watts;
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conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
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/* set max possible time window */
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conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW;
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/* set minimum duty cycle */
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conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE;
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if ((1 << sku) & u42_mask)
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conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
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}
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}
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*pl2_val = pl2;
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conf->tdp_pl2_override = pl2;
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/* set psyspl2 to 90% of max adapter power */
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/* set psyspl2 to 90% of max adapter power */
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*psyspl2_val = SET_PSYSPL2(psyspl2);
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conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
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}
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}
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static uint8_t read_oem_id_from_gpio(void)
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static uint8_t read_oem_id_from_gpio(void)
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@ -282,7 +296,7 @@ static void mainboard_enable(device_t dev)
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device_t root = SA_DEV_ROOT;
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device_t root = SA_DEV_ROOT;
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config_t *conf = root->chip_info;
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config_t *conf = root->chip_info;
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mainboard_set_power_limits(&conf->tdp_pl2_override, &conf->tdp_psyspl2);
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mainboard_set_power_limits(conf);
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set_bj_adapter_limit();
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set_bj_adapter_limit();
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