Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD
Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jens Rottmann
Myles Watson
parent
625a0cb433
commit
c137385404
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@ -5,6 +5,8 @@ choice
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config BOARD_LIPPERT_FRONTRUNNER
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bool "Cool Frontrunner"
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config BOARD_LIPPERT_LITERUNNER_LX
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bool "Cool LiteRunner-LX"
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config BOARD_LIPPERT_ROADRUNNER_LX
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bool "Cool RoadRunner-LX"
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config BOARD_LIPPERT_SPACERUNNER_LX
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@ -13,6 +15,7 @@ config BOARD_LIPPERT_SPACERUNNER_LX
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endchoice
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source "src/mainboard/lippert/frontrunner/Kconfig"
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source "src/mainboard/lippert/literunner-lx/Kconfig"
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source "src/mainboard/lippert/roadrunner-lx/Kconfig"
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source "src/mainboard/lippert/spacerunner-lx/Kconfig"
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@ -0,0 +1,45 @@
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if BOARD_LIPPERT_LITERUNNER_LX
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select SUPERIO_ITE_IT8712F
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select HAVE_DEBUG_SMBUS
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select UDELAY_TSC
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select CACHE_AS_RAM
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# Board is equipped with a 1 MB SPI flash, however, due to limitations
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# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default lippert/literunner-lx
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config MAINBOARD_PART_NUMBER
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string
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default "Cool LiteRunner-LX"
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config IRQ_SLOT_COUNT
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int
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default 5
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config ONBOARD_UARTS_RS485
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bool "Switch on-board serial ports 1 & 2 to RS485"
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default n
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help
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If selected, the first two on-board serial ports will operate in RS485
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mode instead of RS232.
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config ONBOARD_IDE_SLAVE
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bool "Make on-board CF socket act as Slave"
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default n
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help
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If selected, the on-board Compact Flash card socket will act as IDE
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Slave instead of Master.
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endif # BOARD_LIPPERT_LITERUNNER_LX
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,87 @@
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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device pci 1.2 on end # AES
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
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# UARTs, etc IRQs. OK
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register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010
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register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" # 0:host, 1:device
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register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3E8"
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register "com1_irq" = "6"
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register "com2_enable" = "0"
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register "com2_address" = "0x2E8"
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register "com2_irq" = "6"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci 8.0 on end # Ethernet 2
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device pci c.0 on end # IT8888
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device pci d.0 on end # Mini-PCI
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device pci e.0 on end # Ethernet 1
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device pci f.0 on # ISA Bridge
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chip superio/ite/it8712f
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290 # EC
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io 0x62 = 0x298 # PME
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irq 0x70 = 9
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO
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io 0x62 = 0x1220 # Simple I/O
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io 0x64 = 0x1228 # SPI
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.9 off # Game port
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci f.2 on end # IDE
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,73 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/pirq_routing.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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#define PIRQA 10
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#define PIRQB 11
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#define PIRQC 5
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#define PIRQD 15
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0xB8, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1 */
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{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2 */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* Mini-PCI */
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,93 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
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#include <stdlib.h>
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#include <stdint.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
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#if CONFIG_ONBOARD_UARTS_RS485
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#define SIO_GP1X_CONFIG 0x07
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#else
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#define SIO_GP1X_CONFIG 0x01
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#endif
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/* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */
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#define SIO_GP2X_CONFIG 0x00
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static const u16 ec_init_table[] = { /* hi=data, lo=index */
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0x1900, /* Enable monitoring */
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0x3050, /* VIN4,5 enabled */
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0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
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0x805C, /* Unlock zero adjust */
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0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
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0x005C, /* Lock zero adjust */
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0xD014 /* Also set FAN_CTL polarity to Active High */
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};
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static void init(struct device *dev)
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{
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unsigned int gpio_base, i;
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printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__);
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/* Init CS5536 GPIOs */
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gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
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outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
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outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
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outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
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outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
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outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
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outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
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outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
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outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
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/* Init Environment Controller. */
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for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
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u16 val = ec_init_table[i];
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outb((u8)val, 0x0295);
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outb(val >> 8, 0x0296);
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}
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/* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
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outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
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/* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */
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outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */
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printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("LiPPERT LiteRunner-LX Mainboard")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,209 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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/* Based on romstage.c from the SpaceRunner-LX mainboard. */
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#include <stdlib.h>
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#include <stdint.h>
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#include <spd.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/hlt.h>
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#include <console/console.h>
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#include "lib/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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#include "superio/ite/it8712f/it8712f_early_serial.c"
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/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
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#if CONFIG_ONBOARD_IDE_SLAVE
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#define SMC_CONFIG 0x03
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#else
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#define SMC_CONFIG 0x01
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#endif
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#define ManualConf 1 /* No automatic strapped PLL config */
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#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
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#define PLLMSRlo 0x00DE6001
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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|
||||
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
|
||||
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
|
||||
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
|
||||
[SPD_NUM_ROWS] = 0x0D, // Number of row address bits [13]
|
||||
[SPD_NUM_COLUMNS] = 0x0A, // Number of column address bits [10]
|
||||
[SPD_NUM_DIMM_BANKS] = 1, // Number of module rows (banks)
|
||||
0xFF, 0xFF, 0xFF,
|
||||
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x50, // SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD]
|
||||
0xFF, 0xFF,
|
||||
[SPD_REFRESH] = 0x82, // Refresh rate/type [Self Refresh, 7.8 us]
|
||||
[SPD_PRIMARY_SDRAM_WIDTH] = 64, // SDRAM width (primary SDRAM) [64 bits]
|
||||
0xFF, 0xFF, 0xFF,
|
||||
[SPD_NUM_BANKS_PER_SDRAM] = 4, // SDRAM device attributes, number of banks on SDRAM device
|
||||
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, // SDRAM device attributes, CAS latency [3, 2.5, 2]
|
||||
0xFF, 0xFF,
|
||||
[SPD_MODULE_ATTRIBUTES] = 0x20, // SDRAM module attributes [differential clk]
|
||||
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, // SDRAM device attributes, general [Concurrent AP]
|
||||
[SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, // SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD]
|
||||
0xFF,
|
||||
[SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, // SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD]
|
||||
0xFF,
|
||||
[SPD_tRP] = 60, // Min. row precharge time [15 ns in units of 0.25 ns]
|
||||
[SPD_tRRD] = 40, // Min. row active to row active [10 ns in units of 0.25 ns]
|
||||
[SPD_tRCD] = 60, // Min. RAS to CAS delay [15 ns in units of 0.25 ns]
|
||||
[SPD_tRAS] = 40, // Min. RAS pulse width = active to precharge delay [40 ns]
|
||||
[SPD_BANK_DENSITY] = 0x40, // Density of each row on module [256 MB]
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
[SPD_tRFC] = 70 // SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns]
|
||||
};
|
||||
|
||||
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
if (device != DIMM0)
|
||||
return 0xFF; /* No DIMM1, don't even try. */
|
||||
|
||||
#if CONFIG_DEBUG_SMBUS
|
||||
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
|
||||
print_err("ERROR: spd_read_byte(DIMM0, 0x");
|
||||
print_err_hex8(address);
|
||||
print_err(") returns 0xff\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Fake SPD ROM value */
|
||||
return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
|
||||
}
|
||||
|
||||
/* Send config data to System Management Controller via SMB. */
|
||||
static int smc_send_config(unsigned char config_data)
|
||||
{
|
||||
if (smbus_check_stop_condition(SMBUS_IO_BASE))
|
||||
return 1;
|
||||
if (smbus_start_condition(SMBUS_IO_BASE))
|
||||
return 2;
|
||||
if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
|
||||
return 3;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
|
||||
return 4;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
|
||||
return 5;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, config_data))
|
||||
return 6;
|
||||
smbus_stop_condition(SMBUS_IO_BASE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#include "northbridge/amd/lx/raminit.h"
|
||||
#include "northbridge/amd/lx/pll_reset.c"
|
||||
#include "northbridge/amd/lx/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
#include "cpu/amd/model_lx/msrinit.c"
|
||||
|
||||
static const u16 sio_init_table[] = { // hi=data, lo=index
|
||||
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
|
||||
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
|
||||
0x1423, // don't delay PoWeROK1/2
|
||||
0x9072, // watchdog triggers PWROK, counts seconds
|
||||
#if !CONFIG_USE_WATCHDOG_ON_BOOT
|
||||
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
|
||||
#endif
|
||||
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
|
||||
0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
|
||||
0x66B8, 0x0FB9, // enable pullups on SPI, RS485_EN, COM3_R/TX_EN
|
||||
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
|
||||
0x03C1, // enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN
|
||||
0xFFC2, // enable Simple-I/O for GP37-30
|
||||
0x07C8, // config GP12-10 as output
|
||||
0x03C9, // config GP21-20 as output
|
||||
0x2DF5, // map Hw Monitor Thermal Output to GP55
|
||||
0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
|
||||
};
|
||||
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
|
||||
it8712f_enter_conf();
|
||||
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
|
||||
u16 val = sio_init_table[i];
|
||||
outb((u8)val, SIO_INDEX);
|
||||
outb(val >> 8, SIO_DATA);
|
||||
}
|
||||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
int err;
|
||||
post_code(0x01);
|
||||
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/*
|
||||
* Note: Must do this AFTER the early_setup! It is counting on some
|
||||
* early MSR setup for CS5536.
|
||||
*/
|
||||
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
|
||||
if ((err = smc_send_config(SMC_CONFIG))) {
|
||||
print_err("ERROR ");
|
||||
print_err_char('0'+err);
|
||||
print_err(" sending config data to SMC\n");
|
||||
}
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check memory. */
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
|
||||
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
|
||||
return;
|
||||
}
|
||||
Loading…
Reference in New Issue