intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT

Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE,
so it was not entirely set WRPROT cacheable.

Reduces first boot raminit (including training) time by 400ms.

Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17488
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/model_206ax/Kconfig

@@ -25,6 +25,10 @@ config BOOTBLOCK_CPU_INIT
 	string
 	default "cpu/intel/model_206ax/bootblock.c"
 
+config XIP_ROM_SIZE
+	hex
+	default 0x20000 if USE_NATIVE_RAMINIT
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000