mb/system76/oryp6: Convert to variant setup
The Oryx Pro 6 has the same board layout as the next model in series, Oryx Pro 7. The primary difference between the two is the dGPU (20 series to 30 series). Convert oryp6 to a variant setup in preparation for adding the oryp7. Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -27,41 +27,40 @@ config BOARD_SPECIFIC_OPTIONS
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config MAINBOARD_DIR
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default "system76/oryp6"
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config VARIANT_DIR
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default "oryp6" if BOARD_SYSTEM76_ORYP6
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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default "oryp6"
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default "oryp6" if BOARD_SYSTEM76_ORYP6
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Oryx Pro"
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config MAINBOARD_VERSION
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string
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default "oryp6"
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default "oryp6" if BOARD_SYSTEM76_ORYP6
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config CBFS_SIZE
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default 0xA00000
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config CONSOLE_POST
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bool
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default y
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config MAX_CPUS
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int
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default 16
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config DIMM_MAX
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default 2
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config VGA_BIOS_ID
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string
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default "8086,9bc4"
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config POST_DEVICE
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bool
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default n
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endif
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@ -1,9 +1,11 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += gpio_early.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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ramstage-y += hda_verb.c
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ramstage-y += tas5825m.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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@ -1,7 +1,5 @@
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Vendor name: System76
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Board name: oryp6
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Category: laptop
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Release year: 2020
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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@ -1,10 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include <mainboard/gpio.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_init(void)
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{
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mainboard_configure_early_gpios();
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variant_configure_early_gpios();
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}
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@ -57,7 +57,6 @@ chip soc/intel/cannonlake
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end
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device domain 0 on
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subsystemid 0x1558 0x50d3 inherit
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on # GPU Port
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# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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@ -98,7 +97,7 @@ chip soc/intel/cannonlake
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end
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on
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device pci 15.0 on # I2C #0
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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@ -107,7 +106,7 @@ chip soc/intel/cannonlake
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end # I2C #0
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end
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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@ -7,7 +7,7 @@ DefinitionBlock(
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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void mainboard_configure_early_gpios(void);
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void mainboard_configure_gpios(void);
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#endif
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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void variant_configure_early_gpios(void);
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void variant_configure_gpios(void);
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#endif
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@ -1,11 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <mainboard/gpio.h>
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#include <variant/gpio.h>
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static void mainboard_init(void *chip_info)
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{
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mainboard_configure_gpios();
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variant_configure_gpios();
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}
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struct chip_operations mainboard_ops = {
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@ -0,0 +1,2 @@
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Board name: oryp6
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Release year: 2020
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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@ -88,8 +88,8 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
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PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
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//PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
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//PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
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PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
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PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
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PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone
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@ -141,7 +141,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
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//PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
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PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error)
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PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET
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PAD_NC(GPP_F3, NONE),
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@ -163,8 +163,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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/* ------- GPIO Group GPP_G ------- */
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PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
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@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up
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PAD_NC(GPP_H14, NONE),
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PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 20k pull up
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PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
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//PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
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PAD_CFG_GPO(GPP_H17, 1, PLTRST), // TBT_FORCE_PWR_R
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PAD_NC(GPP_H18, NONE),
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PAD_CFG_GPO(GPP_H19, 1, DEEP), // GPIO_CARD_AUX
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@ -242,10 +242,10 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_K5, NONE),
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_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
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PAD_NC(GPP_K7, NONE),
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PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
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PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
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//PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
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//PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
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PAD_CFG_GPO(GPP_K10, 1, DEEP), // LANRTD3_WAKE#
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PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
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//PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
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PAD_NC(GPP_K12, NONE),
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PAD_NC(GPP_K13, NONE),
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PAD_NC(GPP_K14, NONE), // GPP_K_14_GSXDIN (test point)
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PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R
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};
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void mainboard_configure_gpios(void)
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void variant_configure_gpios(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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}
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@ -1,19 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
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PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
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PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
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PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
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PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
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PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
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PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
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PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
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};
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void mainboard_configure_early_gpios(void)
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void variant_configure_early_gpios(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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@ -0,0 +1,5 @@
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chip soc/intel/cannonlake
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device domain 0 on
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subsystemid 0x1558 0x50d3 inherit
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end
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end
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