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mb/system76/oryp6: Convert to variant setup 

The Oryx Pro 6 has the same board layout as the next model in series,
Oryx Pro 7. The primary difference between the two is the dGPU (20
series to 30 series). Convert oryp6 to a variant setup in preparation
for adding the oryp7.

Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Tim Crawford 2021-09-20 12:34:26 -06:00 committed by Patrick Georgi
parent 6dad77d64a
commit c1481e0863
15 changed files with 52 additions and 46 deletions
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17
src/mainboard/system76/oryp6/Kconfig
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@ -27,41 +27,40 @@ config BOARD_SPECIFIC_OPTIONS
config MAINBOARD_DIR
default "system76/oryp6"
config VARIANT_DIR
default "oryp6" if BOARD_SYSTEM76_ORYP6
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "oryp6"
default "oryp6" if BOARD_SYSTEM76_ORYP6
config MAINBOARD_SMBIOS_PRODUCT_NAME
string
default "Oryx Pro"
config MAINBOARD_VERSION
string
default "oryp6"
default "oryp6" if BOARD_SYSTEM76_ORYP6
config CBFS_SIZE
default 0xA00000
config CONSOLE_POST
bool
default y
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config MAX_CPUS
int
default 16
config DIMM_MAX
default 2
config VGA_BIOS_ID
string
default "8086,9bc4"
config POST_DEVICE
bool
default n
endif

8
src/mainboard/system76/oryp6/Makefile.inc
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@ -1,9 +1,11 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += gpio_early.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += romstage.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
ramstage-y += hda_verb.c
ramstage-y += tas5825m.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

2
src/mainboard/system76/oryp6/board_info.txt
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@ -1,7 +1,5 @@
Vendor name: System76
Board name: oryp6
Category: laptop
Release year: 2020
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n

5
src/mainboard/system76/oryp6/bootblock.c
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@ -1,10 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <gpio.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>
void bootblock_mainboard_init(void)
{
mainboard_configure_early_gpios();
variant_configure_early_gpios();
}

5
src/mainboard/system76/oryp6/devicetree.cb
View File

@ -57,7 +57,6 @@ chip soc/intel/cannonlake
end
device domain 0 on
subsystemid 0x1558 0x50d3 inherit
device pci 00.0 on end # Host Bridge
device pci 01.0 on # GPU Port
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
@ -98,7 +97,7 @@ chip soc/intel/cannonlake
end
end
device pci 14.5 off end # SDCard
device pci 15.0 on
device pci 15.0 on # I2C #0
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
@ -107,7 +106,7 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
end
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3

2
src/mainboard/system76/oryp6/dsdt.asl
View File

@ -7,7 +7,7 @@ DefinitionBlock(
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 /* OEM revision */
0x20110725
)
{
#include <acpi/dsdt_top.asl>

9
src/mainboard/system76/oryp6/include/mainboard/gpio.h
View File

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

9
src/mainboard/system76/oryp6/include/variant/gpio.h Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif

4
src/mainboard/system76/oryp6/ramstage.c
View File

@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
variant_configure_gpios();
}
struct chip_operations mainboard_ops = {

2
src/mainboard/system76/oryp6/variants/oryp6/board_info.txt Normal file
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@ -0,0 +1,2 @@
Board name: oryp6
Release year: 2020

0
src/mainboard/system76/oryp6/data.vbt → src/mainboard/system76/oryp6/variants/oryp6/data.vbt
View File

22
src/mainboard/system76/oryp6/gpio.c → src/mainboard/system76/oryp6/variants/oryp6/gpio.c
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
@ -88,8 +88,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
//PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
//PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone
@ -141,7 +141,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
//PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error)
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET
PAD_NC(GPP_F3, NONE),
@ -163,8 +163,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up
PAD_NC(GPP_H14, NONE),
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 20k pull up
PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
//PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_GPO(GPP_H17, 1, PLTRST), // TBT_FORCE_PWR_R
PAD_NC(GPP_H18, NONE),
PAD_CFG_GPO(GPP_H19, 1, DEEP), // GPIO_CARD_AUX
@ -242,10 +242,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_NC(GPP_K7, NONE),
PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
//PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
//PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_GPO(GPP_K10, 1, DEEP), // LANRTD3_WAKE#
PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
//PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
PAD_NC(GPP_K12, NONE),
PAD_NC(GPP_K13, NONE),
PAD_NC(GPP_K14, NONE), // GPP_K_14_GSXDIN (test point)
@ -260,7 +260,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R
};
void mainboard_configure_gpios(void)
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

8
src/mainboard/system76/oryp6/gpio_early.c → src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c
View File

@ -1,19 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3
};
void mainboard_configure_early_gpios(void)
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

0
src/mainboard/system76/oryp6/hda_verb.c → src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c
View File

5
src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb Normal file
View File

@ -0,0 +1,5 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x50d3 inherit
end
end