soc/intel/{common,skylake}: provide common NHLT SoC support

The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides()
functions should be able to be leveraged on all Intel SoCs
which support NHLT. Therefore provide that functionality and
make skylake use it.

Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)

src/soc/intel/common/Kconfig

@@ -99,4 +99,8 @@ config SOC_INTEL_COMMON_ACPI
 	bool
 	default n
 
+config SOC_INTEL_COMMON_NHLT
+	bool
+	default n
+
 endif # SOC_INTEL_COMMON

src/soc/intel/common/Makefile.inc

@@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
 ramstage-y += vbt.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
 
 smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
 

src/soc/intel/skylake/Kconfig

@@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_LPSS_I2C
+	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
 	select SMM_TSEG
 	select SMP

src/soc/intel/skylake/nhlt/Makefile.inc

@@ -1,4 +1,3 @@
-ramstage-y += nhlt.c
 ramstage-y += dmic.c
 ramstage-y += nau88l25.c
 ramstage-y += max98357.c