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mb/google/rex: Add OC pin programming for USB2 Port 8 

This patch adds OC pin programming for USB2 Port 8.

BUG=b:224325352
TEST=Able to build and boot MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-08-08 18:14:54 +00:00
parent a88848907f
commit c15281f91d
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/rex/variants/rex0/overridetree.cb
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@ -4,6 +4,7 @@ chip soc/intel/meteorlake
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth