arm64: mmu: Prevent CPU prefetch instructions from device memory
Set XN bit of block upper attribute to device memory in mmu. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. Set this attribute to device memory mmu entries can prevent CPU from prefetching device memory. BRANCH=none BUG=none TEST=build and booted to kernel on oak-rev3 with dcm enabled. Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302301 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -91,6 +91,7 @@ static uint64_t get_block_attr(unsigned long tag)
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break;
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break;
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case TYPE_DEV_MEM:
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case TYPE_DEV_MEM:
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attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_XN;
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break;
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break;
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case TYPE_DMA_MEM:
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case TYPE_DMA_MEM:
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attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
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@ -72,6 +72,8 @@ extern char _start[], _end[];
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#define BLOCK_ACCESS (1 << 10)
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#define BLOCK_ACCESS (1 << 10)
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#define BLOCK_XN (1UL << 54)
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#define BLOCK_SH_SHIFT (8)
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#define BLOCK_SH_SHIFT (8)
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#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
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@ -76,6 +76,7 @@ static uint64_t get_block_attr(unsigned long tag)
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attr |= BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT;
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} else {
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} else {
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attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
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attr |= BLOCK_XN;
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}
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}
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return attr;
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return attr;
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@ -56,6 +56,8 @@
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#define BLOCK_ACCESS (1 << 10)
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#define BLOCK_ACCESS (1 << 10)
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#define BLOCK_XN (1UL << 54)
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#define BLOCK_SH_SHIFT (8)
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#define BLOCK_SH_SHIFT (8)
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#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
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