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soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions

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Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15672
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:21:12 -05:00
parent e0a49147a6
commit c159bb0d76
2 changed files with 3 additions and 8 deletions
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1
src/soc/intel/fsp_broadwell_de/Kconfig
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@ -7,6 +7,7 @@ if SOC_INTEL_FSP_BROADWELL_DE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32

10
src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
View file

@ -17,6 +17,8 @@
#ifndef _SOC_LPC_H_
#define _SOC_LPC_H_
#include <arch/acpi.h>
/* LPC Interface Bridge PCI Configuration Registers */
#define REVID 0x08
#define PIRQ_RCR1 0x60
@ -49,14 +51,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP_SHIFT 10
#define SLP_TYP (7 << SLP_TYP_SHIFT)
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)