From c17aac32f27f6ab18faaabc8a5667bc2a0a10120 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Wed, 19 Jun 2013 13:12:48 -0500
Subject: [PATCH] lynxpoint: expose iobp functions

The iobp functions are useful to may of the southbridge
devices as certain values need to be updated to properly
initialize the devices. Therefore expose read, write, and
updated iobp functions.

Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59275
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4249
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 src/southbridge/intel/lynxpoint/pch.c | 25 +++++++++++++++++++------
 src/southbridge/intel/lynxpoint/pch.h |  2 ++
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 58c68cdf05..05462c5e74 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -201,7 +201,7 @@ static inline int iobp_poll(void)
 	return 0;
 }
 
-static u32 pch_iobp_read(u32 address)
+u32 pch_iobp_read(u32 address)
 {
 	u16 status;
 
@@ -239,10 +239,15 @@ static u32 pch_iobp_read(u32 address)
 	return RCBA32(IOBPD);
 }
 
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+void pch_iobp_write(u32 address, u32 data)
 {
 	u16 status;
-	u32 data = pch_iobp_read(address);
+
+	if (!iobp_poll())
+		return;
+
+	/* Set the address */
+	RCBA32(IOBPIRI) = address;
 
 	/* WRITE OPCODE */
 	status = RCBA16(IOBPS);
@@ -250,9 +255,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 	status |= IOBPS_WRITE;
 	RCBA16(IOBPS) = status;
 
-	/* Update the data */
-	data &= andvalue;
-	data |= orvalue;
 	RCBA32(IOBPD) = data;
 
 	/* Undocumented magic */
@@ -276,6 +278,17 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 	printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
 }
 
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data = pch_iobp_read(address);
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	pch_iobp_write(address, data);
+}
+
 /* Check if any port in set X to X+3 is enabled */
 static int pch_pcie_check_set_enabled(device_t dev)
 {
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 6ee81d1f4b..c46153ca44 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -162,6 +162,8 @@ void disable_gpe(u32 mask);
 #include <arch/acpi.h>
 #include "chip.h"
 void pch_enable(device_t dev);
+u32 pch_iobp_read(u32 address);
+void pch_iobp_write(u32 address, u32 data);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #if CONFIG_ELOG
 void pch_log_state(void);