more fixes for via ... plus a little more spew.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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303349a9d2
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@ -160,6 +160,7 @@ void hardwaremain(int boot_complete)
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/* If we have already booted attempt a hard reboot */
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if (boot_complete) {
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printk_spew("calling hard_reset\n");
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hard_reset();
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}
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CONFIGURE(CONF_PASS_PRE_PCI);
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@ -50,6 +50,30 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "sdram/generic_sdram.c"
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*/
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static void
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enable_mainboard_devices(void) {
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device_t dev;
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/* dev 0 for southbridge */
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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}
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static void
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enable_shadow_ram(void) {
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(void)
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{
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unsigned long x;
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@ -57,10 +81,12 @@ static void main(void)
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outb(5, 0x80);
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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@ -7,19 +7,26 @@
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*18, /* there can be total 18 devices on the bus */
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1, /* Where the interrupt router lies (bus) */
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0x23, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x0, /* Vendor */
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0x0, /* Device */
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0, /* Crap (miniport) */
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32+16*5, /* there can be total 5 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x88, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x8231, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* 8231 ethernet */
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{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
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/* 8231 internal */
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{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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/* PCI slot */
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{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
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{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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};
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@ -92,7 +92,8 @@ romimage "normal"
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option LINUXBIOS_EXTRA_VERSION=".0Normal"
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mainboard via/epia
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# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
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payload ../../../../tg3--ide_disk.zelf
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# payload ../../../../tg3--ide_disk.zelf
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payload ../../../../../lnxieepro100.ebi
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end
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romimage "fallback"
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@ -101,7 +102,8 @@ romimage "fallback"
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option LINUXBIOS_EXTRA_VERSION=".0Fallback"
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mainboard via/epia
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# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
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payload ../../../../tg3--ide_disk.zelf
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# payload ../../../../tg3--ide_disk.zelf
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payload ../../../../../lnxieepro100.ebi
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end
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buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
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