mainboards/asrock/e350m1: Use driver for Nuvoton NCT5572D superio chip
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot port to this board however used the driver of the Winbond W83627HF SuperIO, which is compatible enough to get most stuff working, but which clears bit 6 in register 0x2B. This switches the function of pin 38 of the NCT5572D from RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the unpopulated miniPCIe slot are connected to this pin, so they didn't get reset during a reboot. Using the newly added driver for the Nuvoton NCT5572D fixes this problem. There is also a trace from the pin 37 of the SuperIO, which can be configured as RSTOUT2#, to pin 82 of the USB3-chip with unknown function. As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB but not in Linux. Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6266 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Felix Held
Nico Huber
parent
16407abddd
commit
c1869666f0
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@ -24,11 +24,6 @@
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#include "SB800.h"
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#include <stdlib.h>
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/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
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*
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* Board is known to have some issues with integrated NIC and
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* might need implementation to drive some GPIOs.
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*/
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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@ -100,6 +95,9 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config
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TempData8 |= Data8;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
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/* this seems to be just copy-pasted from the AMD reference boards and needs
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* some investigation
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*/
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switch(MemData->ParameterListPtr->DDR3Voltage){
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case VOLT1_35:
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Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
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@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_WINBOND_W83627HF
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select SUPERIO_NUVOTON_NCT5572D
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select SB_SUPERIO_HWM
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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@ -54,22 +54,15 @@ chip northbridge/amd/agesa/family14/root_complex
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pci 14.3 on # LPC
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chip superio/nuvoton/nct5572d
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device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
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device pnp 2e.1 off end # LPT1; same as FDC
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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device pnp 2e.3 off # IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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@ -81,19 +74,24 @@ chip northbridge/amd/agesa/family14/root_complex
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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irq 0x70 = 0
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.7 off end # GIPO689
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device pnp 2e.8 off end # WDT
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device pnp 2e.9 off end # GPIO235
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device pnp 2e.a on end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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io 0x62 = 0x0000 # SB-TSI currently not implemented
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irq 0x70 = 5
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end
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device pnp 2e.c off end # PECI
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device pnp 2e.d off end # SUSLED
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device pnp 2e.e off # CIRWKUP
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io 0x60 = 0x0000
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irq 0x70 = 0
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end
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device pnp 2e.f off end # GPIO_PP_OD
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end
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end #LPC
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device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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@ -33,14 +33,14 @@
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#include "agesawrapper.h"
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#include <northbridge/amd/agesa/agesawrapper_call.h>
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#include "cpu/x86/bist.h"
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627hf/w83627hf.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct5572d/nct5572d.h>
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#include "cpu/x86/lapic.h"
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#include <sb_cimx.h>
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#include "SBPLATFORM.h"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sb_Poweron_Init();
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post_code(0x31);
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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