AMD Hudson: show POST codes on a PCI device
Show POST codes on a PCI device: implement hudson_pci_port80(). Remove the comments that use pci_locate_device(): using the code found in the comment seems to break booting. This shares much code with sb600/sb700/sb800, however the deduplication work needs to be discusses somewhere else than in this review board. Tested on an Asus F2A85-M. The contribution is (C) by Rudolf Marek. Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a Author: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4559 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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@ -29,6 +29,51 @@
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#include <cbmem.h>
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#include "hudson.h"
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void hudson_pci_port80(void)
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{
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u8 byte;
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device_t dev;
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/* P2P Bridge */
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dev = PCI_DEV(0, 0x14, 4);
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/* Chip Control: Enable subtractive decoding */
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 5;
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pci_write_config8(dev, 0x40, byte);
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/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 7;
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pci_write_config8(dev, 0x4B, byte);
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/* The same IO Base and IO Limit here is meaningful because we set the
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* bridge to be subtractive. During early setup stage, we have to make
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* sure that data can go through port 0x80.
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*/
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/* IO Base: 0xf000 */
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byte = pci_read_config8(dev, 0x1C);
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byte |= 0xF << 4;
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pci_write_config8(dev, 0x1C, byte);
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/* IO Limit: 0xf000 */
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byte = pci_read_config8(dev, 0x1D);
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byte |= 0xF << 4;
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pci_write_config8(dev, 0x1D, byte);
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/* PCI Command: Enable IO response */
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byte = pci_read_config8(dev, 0x04);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x04, byte);
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/* LPC controller */
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dev = PCI_DEV(0, 0x14, 3);
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byte = pci_read_config8(dev, 0x4A);
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byte &= ~(1 << 5); /* disable lpc port 80 */
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pci_write_config8(dev, 0x4A, byte);
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}
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void hudson_lpc_port80(void)
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{
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u8 byte;
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@ -42,9 +87,9 @@ void hudson_lpc_port80(void)
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outb(byte, 0xCD7);
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
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dev = PCI_DEV(0, 0x14, 3);
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byte = pci_read_config8(dev, 0x4a);
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byte |= 1 << 5; /* enable port 80 */
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byte |= 1 << 5; /* enable port 80 */
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pci_write_config8(dev, 0x4a, byte);
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}
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