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ACPI GNVS: Drop most dev_count_cpu() 

Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.

Remove the PCNT name from GNVS OperationRegion elsewhere.

Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-12-29 05:12:56 +02:00
parent e1383d39d7
commit c196246f75
37 changed files with 20 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/alderlake/acpi.c
View File

@ -285,9 +285,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

3
src/soc/intel/apollolake/acpi.c
View File

@ -80,9 +80,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = cfg->dptf_enable;

2
src/soc/intel/apollolake/acpi/globalnvs.asl
View File

@ -12,7 +12,7 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
PCNT, 8, // 0x00 - Processor Count
, 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State
PWRS, 8, // 0x03 - AC Power State

2
src/soc/intel/apollolake/include/soc/nvs.h
View File

@ -13,7 +13,7 @@
struct __packed global_nvs {
/* Miscellaneous */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
uint8_t lids; /* 0x02 - LID State */
uint8_t pwrs; /* 0x03 - AC Power State */

3
src/soc/intel/baytrail/acpi.c
View File

@ -61,9 +61,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
}

2
src/soc/intel/baytrail/acpi/globalnvs.asl
View File

@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */
PWRS, 8, /* 0x10 - Power State (AC = 1) */
PCNT, 8, /* 0x11 - Processor count */
, 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */
PPCM, 8, /* 0x14 - Maximum P-state usable by OS */

2
src/soc/intel/baytrail/include/soc/nvs.h
View File

@ -21,7 +21,7 @@ struct __packed global_nvs {
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */
u8 pcnt; /* 0x11 - Processor Count */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */

3
src/soc/intel/braswell/acpi.c
View File

@ -64,9 +64,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();

2
src/soc/intel/braswell/acpi/globalnvs.asl
View File

@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */
PWRS, 8, /* 0x10 - Power State (AC = 1) */
PCNT, 8, /* 0x11 - Processor count */
, 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */
PPCM, 8, /* 0x14 - Maximum P-state usable by OS */

2
src/soc/intel/braswell/include/soc/nvs.h
View File

@ -21,7 +21,7 @@ struct __packed global_nvs {
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */
u8 pcnt; /* 0x11 - Processor Count */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */

2
src/soc/intel/broadwell/include/soc/nvs.h
View File

@ -18,7 +18,7 @@ struct __packed global_nvs {
u8 lckf; /* 0x08 - Global Lock function for EC */
u8 prm4; /* 0x09 - Lock function parameter */
u8 prm5; /* 0x0a - Lock function parameter */
u8 pcnt; /* 0x0b - Processor Count */
u8 unused_was_pcnt; /* 0x0b - Processor Count */
u8 ppcm; /* 0x0c - Max PPC State */
u8 tmps; /* 0x0d - Temperature Sensor ID */
u8 tlvl; /* 0x0e - Throttle Level Limit */

2
src/soc/intel/broadwell/pch/acpi/globalnvs.asl
View File

@ -26,7 +26,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
LCKF, 8, // 0x08 - Global Lock function for EC
PRM4, 8, // 0x09 - Lock function parameter
PRM5, 8, // 0x0a - Lock function parameter
PCNT, 8, // 0x0b - Processor Count
, 8, // 0x0b - Processor Count
PPCM, 8, // 0x0c - Max PPC State
TMPS, 8, // 0x0d - Temperature Sensor ID
TLVL, 8, // 0x0e - Throttle Level Limit

3
src/soc/intel/broadwell/pch/lpc.c
View File

@ -604,9 +604,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
}
static unsigned long broadwell_write_acpi_tables(const struct device *device,

3
src/soc/intel/cannonlake/acpi.c
View File

@ -189,9 +189,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

2
src/soc/intel/common/block/acpi/acpi/globalnvs.asl
View File

@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Miscellaneous */
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PCNT, 8, // 0x03 - Processor Count
, 8, // 0x03 - Processor Count
PPCM, 8, // 0x04 - Max PPC State
TLVL, 8, // 0x05 - Throttle Level Limit
LIDS, 8, // 0x06 - LID State

2
src/soc/intel/common/block/include/intelblocks/nvs.h
View File

@ -9,7 +9,7 @@ struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - 0x01 Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
u8 pcnt; /* 0x03 - Processor Count */
u8 unused_was_pcnt; /* 0x03 - Processor Count */
u8 ppcm; /* 0x04 - Max PPC State */
u8 tlvl; /* 0x05 - Throttle Level Limit */
u8 lids; /* 0x06 - LID State */

3
src/soc/intel/denverton_ns/acpi.c
View File

@ -62,9 +62,6 @@ static acpi_cstate_t cstate_map[] = {
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = (uintptr_t)cbmem_top();

2
src/soc/intel/denverton_ns/acpi/globalnvs.asl
View File

@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1)
PCNT, 8, // 0x11 - Processor count
, 8, // 0x11 - Processor count
TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level
PPCM, 8, // 0x14 - Maximum P-state usable by OS

2
src/soc/intel/denverton_ns/include/soc/nvs.h
View File

@ -18,7 +18,7 @@ struct __packed global_nvs {
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */
u8 pcnt; /* 0x11 - Processor Count */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */

3
src/soc/intel/elkhartlake/acpi.c
View File

@ -253,9 +253,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

3
src/soc/intel/icelake/acpi.c
View File

@ -184,9 +184,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

3
src/soc/intel/jasperlake/acpi.c
View File

@ -280,9 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

3
src/soc/intel/skylake/acpi.c
View File

@ -163,9 +163,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

2
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@ -27,7 +27,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
LCKF, 8, // 0x08 - Global Lock function for EC
PRM4, 8, // 0x09 - Lock function parameter
PRM5, 8, // 0x0a - Lock function parameter
PCNT, 8, // 0x0b - Processor Count
, 8, // 0x0b - Processor Count
PPCM, 8, // 0x0c - Max PPC State
TMPS, 8, // 0x0d - Temperature Sensor ID
TLVL, 8, // 0x0e - Throttle Level Limit

2
src/soc/intel/skylake/include/soc/nvs.h
View File

@ -17,7 +17,7 @@ struct __packed global_nvs {
u8 lckf; /* 0x08 - Global Lock function for EC */
u8 prm4; /* 0x09 - Lock function parameter */
u8 prm5; /* 0x0a - Lock function parameter */
u8 pcnt; /* 0x0b - Processor Count */
u8 unused_was_pcnt; /* 0x0b - Processor Count */
u8 ppcm; /* 0x0c - Max PPC State */
u8 tmps; /* 0x0d - Temperature Sensor ID */
u8 tlvl; /* 0x0e - Throttle Level Limit */

3
src/soc/intel/tigerlake/acpi.c
View File

@ -280,9 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

9
src/soc/intel/xeon_sp/cpx/soc_acpi.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <assert.h>
@ -14,7 +13,6 @@
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_util.h>
@ -28,13 +26,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
}
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt);
}
int soc_madt_sci_irq_polarity(int sci)
{
if (sci >= 20)

9
src/soc/intel/xeon_sp/skx/soc_acpi.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <assert.h>
@ -13,7 +12,6 @@
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_util.h>
@ -27,13 +25,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
}
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt);
}
int soc_madt_sci_irq_polarity(int sci)
{
if (sci >= 20)

2
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View File

@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
PCNT, 8, // 0x2d - Processor count
, 8, // 0x2d - Processor count
/* Super I/O & CMOS config */
Offset (0x32),
NATP, 8, // 0x32 -

2
src/southbridge/intel/bd82x6x/include/soc/nvs.h
View File

@ -49,7 +49,7 @@ struct __packed global_nvs {
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
u8 pcnt; /* 0x2d - Processor Count */
u8 unused_was_pcnt; /* 0x2d - Processor Count */
u8 rsvd4[4];
/* Super I/O & CMOS config */
u8 natp; /* 0x32 - SIO type */

1
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -645,7 +645,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
}
static const char *lpc_acpi_name(const struct device *dev)

2
src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
View File

@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
PCNT, 8, // 0x2d - Processor count
, 8, // 0x2d - Processor count
/* Super I/O & CMOS config */
Offset (0x32),
NATP, 8, // 0x32 -

2
src/southbridge/intel/ibexpeak/include/soc/nvs.h
View File

@ -50,7 +50,7 @@ struct __packed global_nvs {
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
u8 pcnt; /* 0x2d - Processor Count */
u8 unused_was_pcnt; /* 0x2d - Processor Count */
u8 rsvd4[4];
/* Super I/O & CMOS config */
u8 natp; /* 0x32 - SIO type */

1
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -545,7 +545,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
}
static const char *lpc_acpi_name(const struct device *dev)

2
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
View File

@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
PCNT, 8, // 0x2d - Processor count
, 8, // 0x2d - Processor count
/* Super I/O & CMOS config */
Offset (0x32),
NATP, 8, // 0x32 -

2
src/southbridge/intel/lynxpoint/include/soc/nvs.h
View File

@ -49,7 +49,7 @@ struct __packed global_nvs {
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
u8 pcnt; /* 0x2d - Processor Count */
u8 unused_was_pcnt; /* 0x2d - Processor Count */
u8 rsvd4[4];
/* Super I/O & CMOS config */
u8 natp; /* 0x32 - SIO type */

1
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -683,7 +683,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
}
static const char *lpc_acpi_name(const struct device *dev)