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haswell: add PCI id support 

In order for coreboot to assign resources properly the pci
drivers need to have th proper device ids. Add the host controller
and the LPC device ids for Lynx Point.

Resource assignment works correctly now w/o odd behavior because
of conflicts.

Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Aaron Durbin 2012-12-11 17:13:17 -06:00 committed by Ronald G. Minnich
parent b6b5aa15ce
commit c1989c494e
4 changed files with 22 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/include/device/pci_ids.h
View File

@ -2600,6 +2600,11 @@
#define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597
#define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599
/* Intel Lynx Point Device IDS */
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 #define PCI_DEVICE_ID_COMPUTONE_PG 0x0302

16
src/northbridge/intel/haswell/northbridge.c
View File

@ -461,22 +461,10 @@ static struct device_operations mc_ops = {
.ops_pci = &intel_pci_ops, .ops_pci = &intel_pci_ops,
}; };
static const struct pci_driver mc_driver_0100 __pci_driver = { static const struct pci_driver mc_driver_hsw_mobile __pci_driver = {
.ops = &mc_ops, .ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0100, .device = 0x0c04, /* Mobile Haswell */
};
static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0104, /* Sandy bridge */
};
static const struct pci_driver mc_driver_1 __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0154, /* Ivy bridge */
}; };
static void cpu_bus_init(device_t dev) static void cpu_bus_init(device_t dev)

21
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -647,15 +647,18 @@ static struct device_operations device_ops = {
}; };
/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
* Intel C200 Series Chipset static const unsigned short pci_device_ids[] = {
*/ 0x8c41, /* Mobile Full Featured Engineering Sample. */
0x8c42, /* Desktop Full Featured Engineering Sample. */
static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, 0x8c44, /* Z87 SKU */
0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x8c46, /* Z85 SKU */
0x1c4f, 0x1c50, 0x1c52, 0x1c54, 0x8c49, /* HM86 SKU */
0x1e55, 0x1c56, 0x1e57, 0x1c5c, 0x8c4a, /* H87 SKU */
0x1e5d, 0x1e5e, 0x1e5f, 0x8c4b, /* HM87 SKU */
0x8c4c, /* Q85 SKU */
0x8c4e, /* Q87 SKU */
0x8c4f, /* QM87 SKU */
0 }; 0 };
static const struct pci_driver pch_lpc __pci_driver = { static const struct pci_driver pch_lpc __pci_driver = {

9
src/southbridge/intel/lynxpoint/spi.c
View File

@ -310,13 +310,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
*/ */
static inline int get_ich_version(uint16_t device_id) static inline int get_ich_version(uint16_t device_id)
{ {
if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) if (device_id >= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN &&
return 7; device_id <= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX)
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
(device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
return 9; return 9;
return 0; return 0;