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mb/google/brya/var/lisbon: update USB topology in devicetree 

update USB topology per the schematic design

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2976028d3efa20e25deedb34ffb8b3bab43b5f5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Kevin Chiu 2022-10-28 16:11:59 +08:00 committed by Felix Held
parent fa5a475206
commit c19a2f09e1
1 changed files with 12 additions and 10 deletions
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22
src/mainboard/google/brya/variants/lisbon/overridetree.cb
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@ -36,17 +36,19 @@ chip soc/intel/alderlake
},
}"
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4
register "usb3_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # USB TYPE C
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,