soc/intel/xeon_sp/acpi: Break out the ACPI PCH IRQ ASL
Continue separating the CPU from the PCH. Move the PCH IRQ ASL from the uncore_irq.asl to a new file, pch_irq.asl. Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Marc Jones
Marc Jones
parent
efb583a6e9
commit
c1ba1d1e15
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@ -0,0 +1,210 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/acpi_asl.h>
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/*
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* PCH devices PCI interrupt routing packages.
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*
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* Note: The PCH routing PR10-PR68 and AR10-AR68 are defined in uncore_irq.asl
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*
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* See ACPI spec 6.2.13 _PRT (PCI routing table) for details.
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* The mapping fields ae Address, Pin, Source, Source Index.
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*/
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// Socket 0, IIOStack 0 device legacy interrupt routing
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Name (PR00, Package ()
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
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// [CB0A]: CBDMA
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// [CB0E]: CBDMA
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Package () { 0x0004FFFF, 0x00, LNKA, 0x00 },
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// [CB0B]: CBDMA
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// [CB0F]: CBDMA
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Package () { 0x0004FFFF, 0x01, LNKB, 0x00 },
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// [CB0C]: CBDMA
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// [CB0G]: CBDMA
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Package () { 0x0004FFFF, 0x02, LNKC, 0x00 },
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// [CB0D]: CBDMA
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// [CB0H]: CBDMA
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Package () { 0x0004FFFF, 0x03, LNKD, 0x00 },
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// Uncore 0 UBOX Device
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Package () { 0x0008FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0008FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0008FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0008FFFF, 0x03, LNKD, 0x00 },
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// [DISP]: Display Controller
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Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
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// [IHC2]: HECI #2
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Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
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// // [XHCI]: xHCI controller 1 on PCH
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Package () { 0x0014FFFF, 0x00, LNKA, 0x00 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package () { 0x0014FFFF, 0x01, LNKB, 0x00 },
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// [TERM]: Thermal Subsystem on PCH
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Package () { 0x0014FFFF, 0x02, LNKC, 0x00 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package () { 0x0014FFFF, 0x03, LNKD, 0x00 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package () { 0x0016FFFF, 0x00, LNKA, 0x00 },
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// [HEC2]: HECI #2 on PCH
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Package () { 0x0016FFFF, 0x01, LNKB, 0x00 },
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// [IDER]: ME IDE redirect on PCH
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Package () { 0x0016FFFF, 0x02, LNKC, 0x00 },
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// [MEKT]: MEKT on PCH
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Package () { 0x0016FFFF, 0x03, LNKD, 0x00 },
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// [SAT1]: SATA controller 1 on PCH
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Package () { 0x0017FFFF, 0x00, LNKA, 0x00 },
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// [NAN1]: NAND Cycle Router on PCH
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Package () { 0x0018FFFF, 0x00, LNKA, 0x00 },
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// [RP17]: PCIE PCH Root Port #17
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Package () { 0x001BFFFF, 0x00, LNKA, 0x00 },
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// [RP18]: PCIE PCH Root Port #18
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Package () { 0x001BFFFF, 0x01, LNKB, 0x00 },
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// [RP19]: PCIE PCH Root Port #19
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Package () { 0x001BFFFF, 0x02, LNKC, 0x00 },
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// [RP20]: PCIE PCH Root Port #20
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Package () { 0x001BFFFF, 0x03, LNKD, 0x00 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package () { 0x001CFFFF, 0x00, LNKA, 0x00 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package () { 0x001CFFFF, 0x01, LNKB, 0x00 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package () { 0x001CFFFF, 0x02, LNKC, 0x00 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package () { 0x001CFFFF, 0x03, LNKD, 0x00 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package () { 0x001DFFFF, 0x00, LNKA, 0x00 },
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// [RP10]: PCIE PCH Root Port #10
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// [RP14]: PCIE PCH Root Port #14
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Package () { 0x001DFFFF, 0x01, LNKB, 0x00 },
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// [RP11]: PCIE PCH Root Port #11
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// [RP15]: PCIE PCH Root Port #15
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Package () { 0x001DFFFF, 0x02, LNKC, 0x00 },
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// [RP12]: PCIE PCH Root Port #12
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// [RP16]: PCIE PCH Root Port #16
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Package () { 0x001DFFFF, 0x03, LNKD, 0x00 },
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// [UAR0]: UART #0 on PCH
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Package () { 0x001EFFFF, 0x02, LNKC, 0x00 },
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// [UAR1]: UART #1 on PCH
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Package () { 0x001EFFFF, 0x03, LNKD, 0x00 },
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// [CAVS]: HD Audio Subsystem Controller on PCH
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// [SMBS]: SMBus controller on PCH
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// [GBE1]: GbE Controller on PCH
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// [NTPK]: Northpeak Controller on PCH
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Package () { 0x001FFFFF, 0x00, LNKA, 0x00 },
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})
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// Socket 0, IIOStack 0 device IOAPIC interrupt routing
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Name (AR00, Package ()
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package () { 0x0000FFFF, 0x00, 0x00, 0x1F },
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// [CB0A]: CB3DMA
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// [CB0E]: CB3DMA
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Package () { 0x0004FFFF, 0x00, 0x00, 0x1A },
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// [CB0B]: CB3DMA
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// [CB0F]: CB3DMA
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Package () { 0x0004FFFF, 0x01, 0x00, 0x1B },
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// [CB0C]: CB3DMA
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// [CB0G]: CB3DMA
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Package () { 0x0004FFFF, 0x02, 0x00, 0x1A },
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// [CB0D]: CB3DMA
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// [CB0H]: CB3DMA
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Package () { 0x0004FFFF, 0x03, 0x00, 0x1B },
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// [UBX0]: Uncore 0 UBOX Device
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Package () { 0x0008FFFF, 0x00, 0x00, 0x18 },
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Package () { 0x0008FFFF, 0x01, 0x00, 0x1C },
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Package () { 0x0008FFFF, 0x02, 0x00, 0x1D },
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Package () { 0x0008FFFF, 0x03, 0x00, 0x1E },
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// [DISP]: Display Controller
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Package () { 0x000FFFFF, 0x00, 0x00, 0x10 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package () { 0x0010FFFF, 0x00, 0x00, 0x10 },
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// [IHC2]: HECI #2
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Package () { 0x0010FFFF, 0x01, 0x00, 0x11 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package () { 0x0010FFFF, 0x02, 0x00, 0x12 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package () { 0x0010FFFF, 0x03, 0x00, 0x13 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package () { 0x0011FFFF, 0x00, 0x00, 0x10 },
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// [XHCI]: xHCI controller 1 on PCH
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Package () { 0x0014FFFF, 0x00, 0x00, 0x10 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package () { 0x0014FFFF, 0x01, 0x00, 0x11 },
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// [TERM]: Thermal Subsystem on PCH
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Package () { 0x0014FFFF, 0x02, 0x00, 0x12 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package () { 0x0014FFFF, 0x03, 0x00, 0x13 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package () { 0x0016FFFF, 0x00, 0x00, 0x10 },
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// [HEC2]: HECI #2 on PCH
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Package () { 0x0016FFFF, 0x01, 0x00, 0x11 },
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// [IDER]: ME IDE redirect on PCH
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Package () { 0x0016FFFF, 0x02, 0x00, 0x12 },
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// [MEKT]: MEKT on PCH
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Package () { 0x0016FFFF, 0x03, 0x00, 0x13 },
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// [SAT1]: SATA controller 1 on PCH
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Package () { 0x0017FFFF, 0x00, 0x00, 0x10 },
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// [NAN1]: NAND Cycle Router on PCH
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Package () { 0x0018FFFF, 0x00, 0x00, 0x10 },
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// [RP17]: PCIE PCH Root Port #17
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Package () { 0x001BFFFF, 0x00, 0x00, 0x10 },
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// [RP18]: PCIE PCH Root Port #18
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Package () { 0x001BFFFF, 0x01, 0x00, 0x11 },
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// [RP19]: PCIE PCH Root Port #19
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Package () { 0x001BFFFF, 0x02, 0x00, 0x12 },
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// [RP20]: PCIE PCH Root Port #20
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Package () { 0x001BFFFF, 0x03, 0x00, 0x13 },
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// [RP01]: PCIE PCH Root Port #1
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// [RP05]: PCIE PCH Root Port #5
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Package () { 0x001CFFFF, 0x00, 0x00, 0x10 },
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// [RP02]: PCIE PCH Root Port #2
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// [RP06]: PCIE PCH Root Port #6
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Package () { 0x001CFFFF, 0x01, 0x00, 0x11 },
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// [RP03]: PCIE PCH Root Port #3
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// [RP07]: PCIE PCH Root Port #7
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Package () { 0x001CFFFF, 0x02, 0x00, 0x12 },
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// [RP04]: PCIE PCH Root Port #4
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// [RP08]: PCIE PCH Root Port #8
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Package () { 0x001CFFFF, 0x03, 0x00, 0x13 },
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// [RP09]: PCIE PCH Root Port #9
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// [RP13]: PCIE PCH Root Port #13
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Package () { 0x001DFFFF, 0x00, 0x00, 0x10 },
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// [RP10]: PCIE PCH Root Port #10
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// [RP14]: PCIE PCH Root Port #14
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Package () { 0x001DFFFF, 0x01, 0x00, 0x11 },
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// [RP11]: PCIE PCH Root Port #11
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// [RP15]: PCIE PCH Root Port #15
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Package () { 0x001DFFFF, 0x02, 0x00, 0x12 },
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// [RP12]: PCIE PCH Root Port #12
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// [RP16]: PCIE PCH Root Port #16
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Package () { 0x001DFFFF, 0x03, 0x00, 0x13 },
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// [UAR0]: UART #0 on PCH
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Package () { 0x001EFFFF, 0x02, 0x00, 0x16 },
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// [UAR1]: UART #1 on PCH
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Package () { 0x001EFFFF, 0x03, 0x00, 0x17 },
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// [CAVS]: HD Audio Subsystem Controller on PCH
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// [SMBS]: SMBus controller on PCH
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// [GBE1]: GbE Controller on PCH
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// [NTPK]: Northpeak Controller on PCH
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Package () { 0x001FFFFF, 0x00, 0x00, 0x10 },
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})
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@ -27,6 +27,7 @@ Scope(\)
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Scope (\_SB)
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Scope (\_SB)
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{
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{
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#include "pci_irqs.asl"
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#include "pci_irqs.asl"
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#include "pch_irq.asl" /* TODO: Move to PCH asl. */
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#include "uncore_irq.asl"
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#include "uncore_irq.asl"
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#include "iiostack.asl"
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#include "iiostack.asl"
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}
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}
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@ -4,208 +4,13 @@
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/*
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/*
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* Uncore devices PCI interrupt routing packages.
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* Uncore devices PCI interrupt routing packages.
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*
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* Note: The PCH routing PR00 and AR00 are defined in pch_irq.asl
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*
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* See ACPI spec 6.2.13 _PRT (PCI routing table) for details.
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* See ACPI spec 6.2.13 _PRT (PCI routing table) for details.
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* The mapping fields ae Address, Pin, Source, Source Index.
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* The mapping fields ae Address, Pin, Source, Source Index.
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*/
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*/
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// Socket 0, IIOStack 0 device legacy interrupt routing
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Name (PR00, Package ()
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
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// [CB0A]: CBDMA
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// [CB0E]: CBDMA
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Package () { 0x0004FFFF, 0x00, LNKA, 0x00 },
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// [CB0B]: CBDMA
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// [CB0F]: CBDMA
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Package () { 0x0004FFFF, 0x01, LNKB, 0x00 },
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// [CB0C]: CBDMA
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// [CB0G]: CBDMA
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Package () { 0x0004FFFF, 0x02, LNKC, 0x00 },
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// [CB0D]: CBDMA
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// [CB0H]: CBDMA
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Package () { 0x0004FFFF, 0x03, LNKD, 0x00 },
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// Uncore 0 UBOX Device
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Package () { 0x0008FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0008FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0008FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0008FFFF, 0x03, LNKD, 0x00 },
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// [DISP]: Display Controller
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Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
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// [IHC2]: HECI #2
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Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
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// // [XHCI]: xHCI controller 1 on PCH
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Package () { 0x0014FFFF, 0x00, LNKA, 0x00 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package () { 0x0014FFFF, 0x01, LNKB, 0x00 },
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// [TERM]: Thermal Subsystem on PCH
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Package () { 0x0014FFFF, 0x02, LNKC, 0x00 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package () { 0x0014FFFF, 0x03, LNKD, 0x00 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package () { 0x0016FFFF, 0x00, LNKA, 0x00 },
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// [HEC2]: HECI #2 on PCH
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Package () { 0x0016FFFF, 0x01, LNKB, 0x00 },
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// [IDER]: ME IDE redirect on PCH
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Package () { 0x0016FFFF, 0x02, LNKC, 0x00 },
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// [MEKT]: MEKT on PCH
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Package () { 0x0016FFFF, 0x03, LNKD, 0x00 },
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// [SAT1]: SATA controller 1 on PCH
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Package () { 0x0017FFFF, 0x00, LNKA, 0x00 },
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// [NAN1]: NAND Cycle Router on PCH
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Package () { 0x0018FFFF, 0x00, LNKA, 0x00 },
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// [RP17]: PCIE PCH Root Port #17
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|
||||||
Package () { 0x001BFFFF, 0x00, LNKA, 0x00 },
|
|
||||||
// [RP18]: PCIE PCH Root Port #18
|
|
||||||
Package () { 0x001BFFFF, 0x01, LNKB, 0x00 },
|
|
||||||
// [RP19]: PCIE PCH Root Port #19
|
|
||||||
Package () { 0x001BFFFF, 0x02, LNKC, 0x00 },
|
|
||||||
// [RP20]: PCIE PCH Root Port #20
|
|
||||||
Package () { 0x001BFFFF, 0x03, LNKD, 0x00 },
|
|
||||||
// [RP01]: PCIE PCH Root Port #1
|
|
||||||
// [RP05]: PCIE PCH Root Port #5
|
|
||||||
Package () { 0x001CFFFF, 0x00, LNKA, 0x00 },
|
|
||||||
// [RP02]: PCIE PCH Root Port #2
|
|
||||||
// [RP06]: PCIE PCH Root Port #6
|
|
||||||
Package () { 0x001CFFFF, 0x01, LNKB, 0x00 },
|
|
||||||
// [RP03]: PCIE PCH Root Port #3
|
|
||||||
// [RP07]: PCIE PCH Root Port #7
|
|
||||||
Package () { 0x001CFFFF, 0x02, LNKC, 0x00 },
|
|
||||||
// [RP04]: PCIE PCH Root Port #4
|
|
||||||
// [RP08]: PCIE PCH Root Port #8
|
|
||||||
Package () { 0x001CFFFF, 0x03, LNKD, 0x00 },
|
|
||||||
// [RP09]: PCIE PCH Root Port #9
|
|
||||||
// [RP13]: PCIE PCH Root Port #13
|
|
||||||
Package () { 0x001DFFFF, 0x00, LNKA, 0x00 },
|
|
||||||
// [RP10]: PCIE PCH Root Port #10
|
|
||||||
// [RP14]: PCIE PCH Root Port #14
|
|
||||||
Package () { 0x001DFFFF, 0x01, LNKB, 0x00 },
|
|
||||||
// [RP11]: PCIE PCH Root Port #11
|
|
||||||
// [RP15]: PCIE PCH Root Port #15
|
|
||||||
Package () { 0x001DFFFF, 0x02, LNKC, 0x00 },
|
|
||||||
// [RP12]: PCIE PCH Root Port #12
|
|
||||||
// [RP16]: PCIE PCH Root Port #16
|
|
||||||
Package () { 0x001DFFFF, 0x03, LNKD, 0x00 },
|
|
||||||
// [UAR0]: UART #0 on PCH
|
|
||||||
Package () { 0x001EFFFF, 0x02, LNKC, 0x00 },
|
|
||||||
// [UAR1]: UART #1 on PCH
|
|
||||||
Package () { 0x001EFFFF, 0x03, LNKD, 0x00 },
|
|
||||||
// [CAVS]: HD Audio Subsystem Controller on PCH
|
|
||||||
// [SMBS]: SMBus controller on PCH
|
|
||||||
// [GBE1]: GbE Controller on PCH
|
|
||||||
// [NTPK]: Northpeak Controller on PCH
|
|
||||||
Package () { 0x001FFFFF, 0x00, LNKA, 0x00 },
|
|
||||||
})
|
|
||||||
|
|
||||||
// Socket 0, IIOStack 0 device IOAPIC interrupt routing
|
|
||||||
Name (AR00, Package ()
|
|
||||||
{
|
|
||||||
// [DMI0]: Legacy PCI Express Port 0
|
|
||||||
Package () { 0x0000FFFF, 0x00, 0x00, 0x1F },
|
|
||||||
// [CB0A]: CB3DMA
|
|
||||||
// [CB0E]: CB3DMA
|
|
||||||
Package () { 0x0004FFFF, 0x00, 0x00, 0x1A },
|
|
||||||
// [CB0B]: CB3DMA
|
|
||||||
// [CB0F]: CB3DMA
|
|
||||||
Package () { 0x0004FFFF, 0x01, 0x00, 0x1B },
|
|
||||||
// [CB0C]: CB3DMA
|
|
||||||
// [CB0G]: CB3DMA
|
|
||||||
Package () { 0x0004FFFF, 0x02, 0x00, 0x1A },
|
|
||||||
// [CB0D]: CB3DMA
|
|
||||||
// [CB0H]: CB3DMA
|
|
||||||
Package () { 0x0004FFFF, 0x03, 0x00, 0x1B },
|
|
||||||
// [UBX0]: Uncore 0 UBOX Device
|
|
||||||
Package () { 0x0008FFFF, 0x00, 0x00, 0x18 },
|
|
||||||
Package () { 0x0008FFFF, 0x01, 0x00, 0x1C },
|
|
||||||
Package () { 0x0008FFFF, 0x02, 0x00, 0x1D },
|
|
||||||
Package () { 0x0008FFFF, 0x03, 0x00, 0x1E },
|
|
||||||
// [DISP]: Display Controller
|
|
||||||
Package () { 0x000FFFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [IHC1]: HECI #1
|
|
||||||
// [IHC3]: HECI #3
|
|
||||||
Package () { 0x0010FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [IHC2]: HECI #2
|
|
||||||
Package () { 0x0010FFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [IIDR]: IDE-Redirection (IDE-R)
|
|
||||||
Package () { 0x0010FFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [IMKT]: Keyboard and Text (KT) Redirection
|
|
||||||
Package () { 0x0010FFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [SAT2]: sSATA Host controller 2 on PCH
|
|
||||||
Package () { 0x0011FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [XHCI]: xHCI controller 1 on PCH
|
|
||||||
Package () { 0x0014FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [OTG0]: USB Device Controller (OTG) on PCH
|
|
||||||
Package () { 0x0014FFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [TERM]: Thermal Subsystem on PCH
|
|
||||||
Package () { 0x0014FFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [CAMR]: Camera IO Host Controller on PCH
|
|
||||||
Package () { 0x0014FFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [HEC1]: HECI #1 on PCH
|
|
||||||
// [HEC3]: HECI #3 on PCH
|
|
||||||
Package () { 0x0016FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [HEC2]: HECI #2 on PCH
|
|
||||||
Package () { 0x0016FFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [IDER]: ME IDE redirect on PCH
|
|
||||||
Package () { 0x0016FFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [MEKT]: MEKT on PCH
|
|
||||||
Package () { 0x0016FFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [SAT1]: SATA controller 1 on PCH
|
|
||||||
Package () { 0x0017FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [NAN1]: NAND Cycle Router on PCH
|
|
||||||
Package () { 0x0018FFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [RP17]: PCIE PCH Root Port #17
|
|
||||||
Package () { 0x001BFFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [RP18]: PCIE PCH Root Port #18
|
|
||||||
Package () { 0x001BFFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [RP19]: PCIE PCH Root Port #19
|
|
||||||
Package () { 0x001BFFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [RP20]: PCIE PCH Root Port #20
|
|
||||||
Package () { 0x001BFFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [RP01]: PCIE PCH Root Port #1
|
|
||||||
// [RP05]: PCIE PCH Root Port #5
|
|
||||||
Package () { 0x001CFFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [RP02]: PCIE PCH Root Port #2
|
|
||||||
// [RP06]: PCIE PCH Root Port #6
|
|
||||||
Package () { 0x001CFFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [RP03]: PCIE PCH Root Port #3
|
|
||||||
// [RP07]: PCIE PCH Root Port #7
|
|
||||||
Package () { 0x001CFFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [RP04]: PCIE PCH Root Port #4
|
|
||||||
// [RP08]: PCIE PCH Root Port #8
|
|
||||||
Package () { 0x001CFFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [RP09]: PCIE PCH Root Port #9
|
|
||||||
// [RP13]: PCIE PCH Root Port #13
|
|
||||||
Package () { 0x001DFFFF, 0x00, 0x00, 0x10 },
|
|
||||||
// [RP10]: PCIE PCH Root Port #10
|
|
||||||
// [RP14]: PCIE PCH Root Port #14
|
|
||||||
Package () { 0x001DFFFF, 0x01, 0x00, 0x11 },
|
|
||||||
// [RP11]: PCIE PCH Root Port #11
|
|
||||||
// [RP15]: PCIE PCH Root Port #15
|
|
||||||
Package () { 0x001DFFFF, 0x02, 0x00, 0x12 },
|
|
||||||
// [RP12]: PCIE PCH Root Port #12
|
|
||||||
// [RP16]: PCIE PCH Root Port #16
|
|
||||||
Package () { 0x001DFFFF, 0x03, 0x00, 0x13 },
|
|
||||||
// [UAR0]: UART #0 on PCH
|
|
||||||
Package () { 0x001EFFFF, 0x02, 0x00, 0x16 },
|
|
||||||
// [UAR1]: UART #1 on PCH
|
|
||||||
Package () { 0x001EFFFF, 0x03, 0x00, 0x17 },
|
|
||||||
// [CAVS]: HD Audio Subsystem Controller on PCH
|
|
||||||
// [SMBS]: SMBus controller on PCH
|
|
||||||
// [GBE1]: GbE Controller on PCH
|
|
||||||
// [NTPK]: Northpeak Controller on PCH
|
|
||||||
Package () { 0x001FFFFF, 0x00, 0x00, 0x10 },
|
|
||||||
})
|
|
||||||
|
|
||||||
// Socket 0, IIOStack 1 device legacy interrupt routing
|
// Socket 0, IIOStack 1 device legacy interrupt routing
|
||||||
Name (PR10, Package ()
|
Name (PR10, Package ()
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue