soc/amd/picasso: Separate GPIO define into gpio_defs.h
Separate GPIO define into gpio_defs.h, then we can use it in asl include. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If2a779eae228f621e77610889205853de2fb179a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Eric Lai
Patrick Georgi
parent
5378219988
commit
c1befbe5d0
3 changed files with 250 additions and 244 deletions
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@ -1,11 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/iomap.h>
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#define GPIO_INPUT_SHIFT 16
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#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT)
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#define GPIO_OUTPUT_SHIFT 22
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#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
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#include <amdblocks/gpio_defs.h>
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/* Get pin control MMIO address */
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Method (GPAD, 0x1)
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@ -4,6 +4,7 @@
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#define AMD_BLOCK_GPIO_BANKS_H
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#include <types.h>
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#include "gpio_defs.h"
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struct soc_amd_gpio {
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uint8_t gpio;
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@ -17,13 +18,6 @@ struct soc_amd_event {
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uint8_t event;
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};
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#define GPIO_MASTER_SWITCH 0xFC
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#define GPIO_MASK_STS_EN BIT(28)
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#define GPIO_INTERRUPT_EN BIT(30)
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#define GPIO_WAKE_EN BIT(31)
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#define GPIO_WAKE_STAT_0 0x2F0
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#define GPIO_WAKE_STAT_1 0x2F4
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struct gpio_wake_state {
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uint32_t control_switch;
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uint32_t wake_stat[2];
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@ -38,59 +32,6 @@ void gpio_fill_wake_state(struct gpio_wake_state *state);
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/* Add gpio events to the eventlog. */
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void gpio_add_events(const struct gpio_wake_state *state);
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#define GPIO_PIN_IN (1 << 0) /* for byte access */
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#define GPIO_PIN_OUT (1 << 6) /* for byte access */
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/* Pad trigger type - Level or Edge */
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#define GPIO_TRIGGER_EDGE (0 << 8)
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#define GPIO_TRIGGER_LEVEL (1 << 8)
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#define GPIO_TRIGGER_MASK (1 << 8)
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/*
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* Pad polarity:
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* Level trigger - High or Low
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* Edge trigger - High (Rising), Low (Falling), Both
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*/
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#define GPIO_ACTIVE_HIGH (0 << 9)
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#define GPIO_ACTIVE_LOW (1 << 9)
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#define GPIO_ACTIVE_BOTH (2 << 9)
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#define GPIO_ACTIVE_MASK (3 << 9)
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/*
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* Pad trigger and polarity configuration.
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* This determines the filtering applied on the input signal at the pad.
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*/
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#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL)
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#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL)
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#define GPIO_INT_ENABLE_STATUS (1 << 11)
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#define GPIO_INT_ENABLE_DELIVERY (1 << 12)
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#define GPIO_INT_ENABLE_STATUS_DELIVERY \
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(GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY)
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#define GPIO_INT_ENABLE_MASK (3 << 11)
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#define GPIO_S0I3_WAKE_EN (1 << 13)
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#define GPIO_S3_WAKE_EN (1 << 14)
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#define GPIO_S4_S5_WAKE_EN (1 << 15)
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#define GPIO_PIN_STS (1 << 16)
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#define GPIO_8KPULLUP_SELECT (1 << 19)
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#define GPIO_PULLUP_ENABLE (1 << 20)
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#define GPIO_PULLDOWN_ENABLE (1 << 21)
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#define GPIO_PULL_MASK (7 << 19)
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#define GPIO_OUTPUT_SHIFT 22
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#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
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#define GPIO_OUTPUT_ENABLE (1 << 23)
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#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT)
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#define GPIO_INT_STATUS (1 << 28)
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#define GPIO_WAKE_STATUS (1 << 29)
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#define GPIO_STATUS_MASK (3 << 28)
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enum {
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GEVENT_0,
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GEVENT_1,
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@ -126,39 +67,6 @@ enum {
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GEVENT_31,
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};
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#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE)
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#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE
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#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT)
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#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE
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#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE
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#define GPIO_PULL_PULL_NONE 0
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#define AMD_GPIO_MUX_MASK 0x03
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/*
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* Flags used for GPIO configuration. These provide additional information that does not go
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* directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio.
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*/
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#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0)
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#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0)
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#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0)
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#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1)
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#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1)
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#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1)
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#define GPIO_FLAG_SCI (1 << 2)
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#define GPIO_FLAG_SMI (1 << 3)
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/* Trigger configuration for GPIO SCI/SMI events. */
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#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \
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GPIO_FLAG_EVENT_ACTIVE_HIGH)
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#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \
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GPIO_FLAG_EVENT_ACTIVE_LOW)
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#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \
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GPIO_FLAG_EVENT_ACTIVE_HIGH)
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#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \
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GPIO_FLAG_EVENT_ACTIVE_LOW)
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static inline bool is_gpio_event_level_triggered(uint32_t flags)
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{
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return (flags & GPIO_FLAG_EVENT_TRIGGER_MASK) == GPIO_FLAG_EVENT_TRIGGER_LEVEL;
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@ -179,152 +87,6 @@ static inline bool is_gpio_event_active_low(uint32_t flags)
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return (flags & GPIO_FLAG_EVENT_ACTIVE_MASK) == GPIO_FLAG_EVENT_ACTIVE_LOW;
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}
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#define DEB_GLITCH_SHIFT 5
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#define DEB_GLITCH_LOW 1
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#define DEB_GLITCH_HIGH 2
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#define DEB_GLITCH_NONE 3
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#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT)
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#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT)
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#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT)
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#define GPIO_TIMEBASE_61uS 0
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#define GPIO_TIMEBASE_183uS (1 << 4)
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#define GPIO_TIMEBASE_15560uS (1 << 7)
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#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \
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GPIO_TIMEBASE_15560uS)
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#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS)
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#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS)
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#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS)
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#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS)
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#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS)
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#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS)
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#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS)
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#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS)
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#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS)
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#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS)
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#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS)
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#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS)
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#define GPIO_DEB_MASK 0xff
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#define GPIO_WAKE_S0i3 (1 << 13)
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#define GPIO_WAKE_S3 (1 << 14)
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#define GPIO_WAKE_S4_S5 (1 << 15)
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#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5)
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#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5)
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#define GPIO_WAKE_MASK (7 << 13)
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/*
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* Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()`
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* Bits that are preserved/untouched:
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* - Reserved bits
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* - Drive strength bits
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* - Read only bits
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*/
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#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \
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GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \
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GPIO_OUTPUT_MASK | GPIO_STATUS_MASK)
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/*
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* Several macros are available to declare programming of GPIO pins. The defined macros and
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* their parameters are:
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* PAD_NF Define native alternate function for the pin.
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* pin the pin to be programmed
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* function the native function
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* pull pull up, pull down or no pull
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* PAD_GPI The pin is a GPIO input
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* PAD_GPO The pin is a GPIO output
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* pin the pin to be programmed
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* direction high or low
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* PAD_INT The pin is regular interrupt that works while booting
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES
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* action STATUS, DELIVER, STATUS_DELIVER
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* PAD_SCI The pin is a SCI source
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH
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* PAD_SMI The pin is a SMI source
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* event trigger LEVEL_LOW, LEVEL_HIGH
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* PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES
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* type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid)
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* PAD_DEBOUNCE The input or interrupt will be debounced
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* pin the pin to be programmed
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* pull pull up, pull down or no pull
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* debounce_type preserve low glitch, preserve high glitch, no glitch
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* debounce_time the debounce time
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*/
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#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \
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{ \
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.gpio = __pin, \
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.function = __function, \
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.control = __control, \
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.flags = __flags, \
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}
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#define PAD_CFG_STRUCT(__pin, __function, __control) \
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PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0)
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#define PAD_PULL(__pull) GPIO_PULL_ ## __pull
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#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir
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#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig
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#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action
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#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig
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#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake
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#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb
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/* Native function pad configuration */
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#define PAD_NF(pin, func, pull) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull))
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/* General purpose input pad configuration */
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#define PAD_GPI(pin, pull) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull))
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/* General purpose output pad configuration */
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#define PAD_GPO(pin, direction) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction))
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/* Legacy interrupt pad configuration */
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#define PAD_INT(pin, pull, trigger, action) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
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PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action))
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/* SCI pad configuration */
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#define PAD_SCI(pin, pull, trigger) \
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PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \
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PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \
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PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI)
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/* SMI pad configuration */
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#define PAD_SMI(pin, pull, trigger) \
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PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \
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PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \
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PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI)
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/* WAKE pad configuration */
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#define PAD_WAKE(pin, pull, trigger, type) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
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PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type))
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/* pin debounce configuration */
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#define PAD_DEBOUNCE(pin, pull, type, time) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
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PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time))
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/* No-connect pad - configured as input with PULL_DOWN */
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#define PAD_NC(pin) \
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PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN))
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typedef uint32_t gpio_t;
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/*
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248
src/soc/amd/common/block/include/amdblocks/gpio_defs.h
Normal file
248
src/soc/amd/common/block/include/amdblocks/gpio_defs.h
Normal file
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@ -0,0 +1,248 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_BLOCK_GPIO_DEFS_H
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#define AMD_BLOCK_GPIO_DEFS_H
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#define GPIO_MASTER_SWITCH 0xFC
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#define GPIO_MASK_STS_EN BIT(28)
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#define GPIO_INTERRUPT_EN BIT(30)
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#define GPIO_WAKE_EN BIT(31)
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#define GPIO_WAKE_STAT_0 0x2F0
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#define GPIO_WAKE_STAT_1 0x2F4
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#define GPIO_PIN_IN (1 << 0) /* for byte access */
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#define GPIO_PIN_OUT (1 << 6) /* for byte access */
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/* Pad trigger type - Level or Edge */
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#define GPIO_TRIGGER_EDGE (0 << 8)
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#define GPIO_TRIGGER_LEVEL (1 << 8)
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#define GPIO_TRIGGER_MASK (1 << 8)
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/*
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* Pad polarity:
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* Level trigger - High or Low
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* Edge trigger - High (Rising), Low (Falling), Both
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*/
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#define GPIO_ACTIVE_HIGH (0 << 9)
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#define GPIO_ACTIVE_LOW (1 << 9)
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#define GPIO_ACTIVE_BOTH (2 << 9)
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#define GPIO_ACTIVE_MASK (3 << 9)
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/*
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* Pad trigger and polarity configuration.
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* This determines the filtering applied on the input signal at the pad.
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*/
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#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE)
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#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL)
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#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL)
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#define GPIO_INT_ENABLE_STATUS (1 << 11)
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#define GPIO_INT_ENABLE_DELIVERY (1 << 12)
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#define GPIO_INT_ENABLE_STATUS_DELIVERY \
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(GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY)
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#define GPIO_INT_ENABLE_MASK (3 << 11)
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#define GPIO_S0I3_WAKE_EN (1 << 13)
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#define GPIO_S3_WAKE_EN (1 << 14)
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#define GPIO_S4_S5_WAKE_EN (1 << 15)
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#define GPIO_PIN_STS (1 << 16)
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#define GPIO_8KPULLUP_SELECT (1 << 19)
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#define GPIO_PULLUP_ENABLE (1 << 20)
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#define GPIO_PULLDOWN_ENABLE (1 << 21)
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#define GPIO_PULL_MASK (7 << 19)
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#define GPIO_INPUT_SHIFT 16
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#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT)
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#define GPIO_OUTPUT_SHIFT 22
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#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
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#define GPIO_OUTPUT_ENABLE (1 << 23)
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#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT)
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#define GPIO_INT_STATUS (1 << 28)
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#define GPIO_WAKE_STATUS (1 << 29)
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#define GPIO_STATUS_MASK (3 << 28)
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#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE)
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#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE
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#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT)
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#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE
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#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE
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#define GPIO_PULL_PULL_NONE 0
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#define AMD_GPIO_MUX_MASK 0x03
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/*
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* Flags used for GPIO configuration. These provide additional information that does not go
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* directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio.
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*/
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#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0)
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#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0)
|
||||
#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0)
|
||||
#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1)
|
||||
#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1)
|
||||
#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1)
|
||||
#define GPIO_FLAG_SCI (1 << 2)
|
||||
#define GPIO_FLAG_SMI (1 << 3)
|
||||
|
||||
/* Trigger configuration for GPIO SCI/SMI events. */
|
||||
#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \
|
||||
GPIO_FLAG_EVENT_ACTIVE_HIGH)
|
||||
#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \
|
||||
GPIO_FLAG_EVENT_ACTIVE_LOW)
|
||||
#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \
|
||||
GPIO_FLAG_EVENT_ACTIVE_HIGH)
|
||||
#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \
|
||||
GPIO_FLAG_EVENT_ACTIVE_LOW)
|
||||
#define DEB_GLITCH_SHIFT 5
|
||||
#define DEB_GLITCH_LOW 1
|
||||
#define DEB_GLITCH_HIGH 2
|
||||
#define DEB_GLITCH_NONE 3
|
||||
#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT)
|
||||
#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT)
|
||||
#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT)
|
||||
|
||||
#define GPIO_TIMEBASE_61uS 0
|
||||
#define GPIO_TIMEBASE_183uS (1 << 4)
|
||||
#define GPIO_TIMEBASE_15560uS (1 << 7)
|
||||
#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \
|
||||
GPIO_TIMEBASE_15560uS)
|
||||
#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS)
|
||||
#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS)
|
||||
#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS)
|
||||
#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS)
|
||||
#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS)
|
||||
#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS)
|
||||
#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS)
|
||||
#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS)
|
||||
#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS)
|
||||
#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS)
|
||||
#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS)
|
||||
#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS)
|
||||
|
||||
#define GPIO_DEB_MASK 0xff
|
||||
|
||||
#define GPIO_WAKE_S0i3 (1 << 13)
|
||||
#define GPIO_WAKE_S3 (1 << 14)
|
||||
#define GPIO_WAKE_S4_S5 (1 << 15)
|
||||
#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5)
|
||||
#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5)
|
||||
#define GPIO_WAKE_MASK (7 << 13)
|
||||
|
||||
/*
|
||||
* Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()`
|
||||
* Bits that are preserved/untouched:
|
||||
* - Reserved bits
|
||||
* - Drive strength bits
|
||||
* - Read only bits
|
||||
*/
|
||||
#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \
|
||||
GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \
|
||||
GPIO_OUTPUT_MASK | GPIO_STATUS_MASK)
|
||||
|
||||
/*
|
||||
* Several macros are available to declare programming of GPIO pins. The defined macros and
|
||||
* their parameters are:
|
||||
* PAD_NF Define native alternate function for the pin.
|
||||
* pin the pin to be programmed
|
||||
* function the native function
|
||||
* pull pull up, pull down or no pull
|
||||
* PAD_GPI The pin is a GPIO input
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* PAD_GPO The pin is a GPIO output
|
||||
* pin the pin to be programmed
|
||||
* direction high or low
|
||||
* PAD_INT The pin is regular interrupt that works while booting
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES
|
||||
* action STATUS, DELIVER, STATUS_DELIVER
|
||||
* PAD_SCI The pin is a SCI source
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH
|
||||
* PAD_SMI The pin is a SMI source
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* event trigger LEVEL_LOW, LEVEL_HIGH
|
||||
* PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES
|
||||
* type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid)
|
||||
* PAD_DEBOUNCE The input or interrupt will be debounced
|
||||
* pin the pin to be programmed
|
||||
* pull pull up, pull down or no pull
|
||||
* debounce_type preserve low glitch, preserve high glitch, no glitch
|
||||
* debounce_time the debounce time
|
||||
*/
|
||||
|
||||
#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \
|
||||
{ \
|
||||
.gpio = __pin, \
|
||||
.function = __function, \
|
||||
.control = __control, \
|
||||
.flags = __flags, \
|
||||
}
|
||||
|
||||
#define PAD_CFG_STRUCT(__pin, __function, __control) \
|
||||
PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0)
|
||||
|
||||
#define PAD_PULL(__pull) GPIO_PULL_ ## __pull
|
||||
#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir
|
||||
#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig
|
||||
#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action
|
||||
#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig
|
||||
#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake
|
||||
#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb
|
||||
|
||||
/* Native function pad configuration */
|
||||
#define PAD_NF(pin, func, pull) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull))
|
||||
|
||||
/* General purpose input pad configuration */
|
||||
#define PAD_GPI(pin, pull) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull))
|
||||
|
||||
/* General purpose output pad configuration */
|
||||
#define PAD_GPO(pin, direction) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction))
|
||||
|
||||
/* Legacy interrupt pad configuration */
|
||||
#define PAD_INT(pin, pull, trigger, action) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
|
||||
PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action))
|
||||
|
||||
/* SCI pad configuration */
|
||||
#define PAD_SCI(pin, pull, trigger) \
|
||||
PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \
|
||||
PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \
|
||||
PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI)
|
||||
|
||||
/* SMI pad configuration */
|
||||
#define PAD_SMI(pin, pull, trigger) \
|
||||
PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \
|
||||
PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \
|
||||
PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI)
|
||||
|
||||
/* WAKE pad configuration */
|
||||
#define PAD_WAKE(pin, pull, trigger, type) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
|
||||
PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type))
|
||||
|
||||
/* pin debounce configuration */
|
||||
#define PAD_DEBOUNCE(pin, pull, type, time) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \
|
||||
PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time))
|
||||
|
||||
/* No-connect pad - configured as input with PULL_DOWN */
|
||||
#define PAD_NC(pin) \
|
||||
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN))
|
||||
|
||||
#endif /* AMD_BLOCK_GPIO_DEFS_H */
|
||||
Loading…
Reference in a new issue