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Falco: Patch to enable correct port clock selection for dp 

This is required only for haswell since the register configs have changed.
Also, created mainboard specific header file

Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945
Signed-off-by: Furquan Shaikh <furquan@google.com>

Conflicts:
	src/mainboard/google/slippy/gma.c
	src/mainboard/google/slippy/i915io.c

Conflicts:
	src/mainboard/google/slippy/gma.c
Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5
Reviewed-on: https://gerrit.chromium.org/gerrit/66853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6602
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Furquan Shaikh 2013-08-06 13:48:12 -07:00 committed by Isaac Christensen
parent 77f48cdead
commit c1c6dcf0f3
3 changed files with 51 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/mainboard/google/slippy/gma.c
View File

@ -43,6 +43,7 @@
#include <cpu/x86/msr.h>
#include <edid.h>
#include <drivers/intel/gma/i915.h>
#include "mainboard.h"
/*
* Here is the rough outline of how we bring up the display:
@ -228,7 +229,6 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw)
}
}
void mainboard_train_link(struct intel_dp *intel_dp);
void mainboard_train_link(struct intel_dp *intel_dp)
{
u8 read_val;
@ -281,6 +281,29 @@ static void test_gfx(struct intel_dp *dp)
static void test_gfx(struct intel_dp *dp) {}
#endif
void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
{
u32 ddi_pll_sel = 0;
switch (intel_dp->link_bw) {
case DP_LINK_BW_1_62:
ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
break;
case DP_LINK_BW_2_7:
ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
break;
case DP_LINK_BW_5_4:
ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
break;
default:
printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
return;
}
gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
}
int i915lightup(unsigned int pphysbase, unsigned int pmmio,
unsigned int pgfx, unsigned int init_fb)
{

5
src/mainboard/google/slippy/i915io.c
View File

@ -26,6 +26,7 @@
#include <delay.h>
#include <drivers/intel/gma/i915.h>
#include <arch/io.h>
#include "mainboard.h"
/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
int index;
@ -33,8 +34,6 @@ u32 auxout;
u8 auxin[20];
u8 msg[32];
extern void mainboard_train_link(struct intel_dp *intel_dp);
/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
void runio(struct intel_dp *dp);
@ -71,7 +70,7 @@ void runio(struct intel_dp *dp)
gtt_write(PIPECONF(dp->transcoder),0x00000000);
gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
gtt_write(PORT_CLK_SEL(dp->port),PORT_CLK_SEL_LCPLL_1350);
mainboard_set_port_clk_dp(dp);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
gtt_write(DEIIR,0x00000080);

25
src/mainboard/google/slippy/mainboard.h Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_H_
#define __MAINBOARD_H_
void mainboard_train_link(struct intel_dp *intel_dp);
void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
#endif