mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers

Rework gpio setup for the board series to not use headers but
stage-specific compilation units.

Tested successfully on X11SSM-F.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Michael Niewöhner 2020-11-24 13:49:11 +01:00
parent e88dacfa43
commit c1d1dddbcc
10 changed files with 100 additions and 70 deletions

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@ -1,10 +1,11 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
ramstage-y += mainboard.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
ramstage-y += mainboard.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

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@ -1,20 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
#include <mainboard/gpio.h>
#include <superio/aspeed/common/aspeed.h>
#include <superio/aspeed/ast2400/ast2400.h>
#include <console/uart.h>
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
* which it shouldn't do. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
static void early_config_superio(void)
{
const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
@ -23,6 +14,6 @@ static void early_config_superio(void)
void bootblock_mainboard_early_init(void)
{
early_config_gpio();
mainboard_configure_early_gpios();
early_config_superio();
}

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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

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@ -2,8 +2,7 @@
#include <mainboard.h>
#include <device/device.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <mainboard/gpio.h>
__weak void variant_mainboard_init(void *chip_info)
{
@ -12,7 +11,7 @@ __weak void variant_mainboard_init(void *chip_info)
static void mainboard_chip_init(void *chip_info)
{
/* do common init */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
mainboard_configure_gpios();
/* do variant init */
variant_mainboard_init(chip_info);

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@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _GPIO_X11SSH_F_H
#define _GPIO_X11SSH_F_H
#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -226,17 +224,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
};
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};
#endif /* _GPIO_X11SSH_F_H */
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _GPIO_X11SSH_TF_H
#define _GPIO_X11SSH_TF_H
#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -226,17 +224,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
};
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};
#endif /* _GPIO_X11SSH_TF_H */
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _GPIO_X11SSM_F_H
#define _GPIO_X11SSM_F_H
#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -232,17 +230,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPD11, NONE),
};
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
};
#endif /* _GPIO_X11SSM_F_H */
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}