diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 02785bcdd0..83039a8c81 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -27,6 +27,7 @@ static void mch_domain_read_resources(struct device *dev)
 {
 	u64 tom, touud;
 	u32 tomk, tolud, uma_sizek = 0, delta_cbmem;
+	int idx = 3;
 
 	/* Total Memory 2GB example:
 	 *
@@ -102,7 +103,7 @@ static void mch_domain_read_resources(struct device *dev)
 	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
 
 	/* Report lowest memory region */
-	ram_resource(dev, 3, 0, 0xa0000 / KiB);
+	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
 
 	/*
 	 * Reserve everything between A segment and 1MB:
@@ -110,11 +111,11 @@ static void mch_domain_read_resources(struct device *dev)
 	 * 0xa0000 - 0xbffff: Legacy VGA
 	 * 0xc0000 - 0xfffff: RAM
 	 */
-	mmio_resource(dev, 4, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
-	reserved_ram_resource(dev, 5, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
+	mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
 
 	/* Report < 4GB memory */
-	ram_resource(dev, 6, 1*MiB / KiB, tomk - 1*MiB / KiB);
+	ram_resource(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB);
 
 	/*
 	 * If >= 4GB installed then memory from TOLUD to 4GB
@@ -122,7 +123,7 @@ static void mch_domain_read_resources(struct device *dev)
 	 */
 	touud >>= 10; /* Convert to KB */
 	if (touud > 4096 * 1024) {
-		ram_resource(dev, 7, 4096 * 1024, touud - (4096 * 1024));
+		ram_resource(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
 		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
 		       (touud >> 10) - 4096);
 	}
@@ -130,9 +131,9 @@ static void mch_domain_read_resources(struct device *dev)
 	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
 	       "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
 	/* Don't use uma_resource() as our UMA touches the PCI hole. */
-	fixed_mem_resource(dev, 8, tomk, uma_sizek, IORESOURCE_RESERVE);
+	fixed_mem_resource(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE);
 
-	mmconf_resource(dev, 9);
+	mmconf_resource(dev, idx++);
 }
 
 static void mch_domain_set_resources(struct device *dev)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 4909143a1f..a111378fd8 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -21,6 +21,7 @@ static void mch_domain_read_resources(struct device *dev)
 	uint64_t uma_memory_base = 0, uma_memory_size = 0;
 	uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
 	struct device *const d0f0 = pcidev_on_root(0, 0);
+	int idx = 3;
 
 	pci_domain_read_resources(dev);
 
@@ -74,15 +75,15 @@ static void mch_domain_read_resources(struct device *dev)
 	printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen / KiB));
 
 	/* Report the memory regions */
-	ram_resource(dev, 3, 0, 0xa0000 / KiB);
-	ram_resource(dev, 4, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
-	uma_resource(dev, 5, uma_memory_base / KiB, uma_memory_size / KiB);
-	mmio_resource(dev, 6, tseg_memory_base / KiB, tseg_memory_size / KiB);
-	uma_resource(dev, 7, cbmem_topk, delta_cbmem);
+	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+	ram_resource(dev, idx++, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
+	uma_resource(dev, idx++, uma_memory_base / KiB, uma_memory_size / KiB);
+	mmio_resource(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
+	uma_resource(dev, idx++, cbmem_topk, delta_cbmem);
 	/* legacy VGA memory */
-	mmio_resource(dev, 8, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+	mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
 	/* RAM to be used for option roms and BIOS */
-	reserved_ram_resource(dev, 9, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
+	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
 }
 
 static void mch_domain_set_resources(struct device *dev)