+ Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + here. + The development steps for the board are listed below: +
++ Create the board directory as src/mainboard/<Vendor>/<Board>. +
+ ++ The following files are required to build a new board: +
+Modified: 31 January 2016
+ + \ No newline at end of file diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html new file mode 100644 index 0000000000..210a821b41 --- /dev/null +++ b/Documentation/Intel/Board/galileo.html @@ -0,0 +1,100 @@ + + + + |
+
+
+ The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + Quark™ SoC: + + + |
+
Modified: 30 January 2016
+ + diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html new file mode 100644 index 0000000000..14dd5076b3 --- /dev/null +++ b/Documentation/Intel/SoC/quark.html @@ -0,0 +1,98 @@ + + + + |
+
+
+ The Quark™ SoC code was developed using the + Galileo Gen 2 + board: + + + |
+
set WORKSPACE=%CD%
+set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+cd edk2
+edksetup.bat
+build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+Modified: 30 January 2016
+ + \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html new file mode 100644 index 0000000000..30821dcd9c --- /dev/null +++ b/Documentation/Intel/SoC/soc.html @@ -0,0 +1,105 @@ + + + ++ SoC development is best done in parallel with development for a specific + board. The combined steps are listed + here. + The development steps for the SoC are listed below: +
++ Create the directory as src/soc/<Vendor>/<Chip Family>. +
+ ++ The following files are required to build a new SoC: +
++ Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +
+ ++ The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +
+dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1+ Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +
+util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
+mv build/coreboot.rom.new build/coreboot.rom
++ Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +
+ + ++ When the reset vector is successfully invoked, port 0x80 will output the following value: +
+Modified: 31 January 2016
+ + \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html new file mode 100644 index 0000000000..1dbef9cbda --- /dev/null +++ b/Documentation/Intel/development.html @@ -0,0 +1,78 @@ + + + ++ The x86 development process for coreboot is broken into the following components: +
+ ++ The development process has two main phases: +
++ The combined steps below describe how to bring up a minimal coreboot for a + system-on-a-chip (SoC) and a development board: +
+| The initial coreboot steps are single threaded! + The initial minimal FSP development is also single threaded. + Progress can speed up by adding more developers after the minimal coreboot/FSP + implementation reaches the payload. + | +
sudo apt-get install m4 bison flex libncurses5-dev
+make crossgcc-i386make crossgcc-i386 CPUS=NModified: 31 January 2016
+ + \ No newline at end of file diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html new file mode 100644 index 0000000000..c210ffb89c --- /dev/null +++ b/Documentation/Intel/fsp1_1.html @@ -0,0 +1,50 @@ + + + ++ Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) + and board support. The combined steps are listed + here. + The development steps for FSP are listed below: +
++ FSP Documentation: +
+Modified: 31 January 2016
+ + \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html new file mode 100644 index 0000000000..6d5810f110 --- /dev/null +++ b/Documentation/Intel/index.html @@ -0,0 +1,42 @@ + + + +Modified: 31 January 2016
+ + \ No newline at end of file