diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 4297f903b0..2e32b28919 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -112,8 +112,8 @@ chip soc/amd/mendocino
 
 		register "dxio_tx_vboost_enable" = "1"
 
-		# The unit is set to one per 4ms
-		register "pwr_on_vary_bl_to_blon" = "0x1c"
+		# The unit is set to one per ms
+		register "edp_panel_t8_ms" = "112"
 
 		device ref gpp_bridge_1 on
 			# Required so the NVMe gets placed into D3 when entering S0i3.
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index 774ce5ea59..5eb7c41cb7 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -177,9 +177,8 @@ struct soc_amd_mendocino_config {
 	/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
 	union usb3_force_gen1 usb3_port_force_gen1;
 
-	/* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to
-	   one per 4ms*/
-	uint8_t pwr_on_vary_bl_to_blon;
+	/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
+	uint8_t edp_panel_t8_ms;
 
 };
 
diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c
index 453ce69788..cea26a9acd 100644
--- a/src/soc/amd/mendocino/fsp_m_params.c
+++ b/src/soc/amd/mendocino/fsp_m_params.c
@@ -170,7 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	}
 
 	mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
-	mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon;
+	mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
 
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 	fsp_assign_ioapic_upds(mcfg);
diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
index 391c64b822..b3d6dc39d9 100644
--- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
@@ -101,8 +101,8 @@ typedef struct __packed {
 	/** Offset 0x04E1**/	uint32_t                    vrm_maximum_current_limit_mA;
 	/** Offset 0x04E5**/	uint32_t                    vrm_soc_current_limit_mA;
 	/** Offset 0x04E9**/	uint8_t                     fch_usb_3_port_force_gen1;
-	/** Offset 0x04E9**/	uint8_t                     pwr_on_vary_bl_to_blon;
-	/** Offset 0x04EA**/	uint8_t                     UnusedUpdSpace2[277];
+	/** Offset 0x04EA**/	uint8_t                     edp_panel_t8_ms;
+	/** Offset 0x04EB**/	uint8_t                     UnusedUpdSpace2[277];
 	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;