diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c
index 703b74b821..6d0d0d6ff9 100644
--- a/src/mainboard/google/myst/port_descriptors.c
+++ b/src/mainboard/google/myst/port_descriptors.c
@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
 #include <gpio.h>
 #include <soc/platform_descriptors.h>
 #include <types.h>
 
-static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
-	{ /* WWAN */
+static fsp_dxio_descriptor myst_dxio_descriptors[] = {
+	[DXIO_WWAN] = {
 		.engine_type = UNUSED_ENGINE,
 		.port_present = true,
 		.start_logical_lane = 13,
@@ -17,7 +19,7 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ2,
 	},
-	{ /* WLAN */
+	[DXIO_WLAN] = {
 		.engine_type = PCIE_ENGINE,
 		.port_present = true,
 		.start_logical_lane = 14,
@@ -28,7 +30,7 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ0,
 	},
-	{ /*  SD */
+	[DXIO_SD] = {
 		.engine_type = PCIE_ENGINE,
 		.port_present = true,
 		.start_logical_lane = 15,
@@ -40,17 +42,31 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
 		.link_hotplug = 3,
 		.clk_req = CLK_REQ1,
 	},
-	{ /* SSD */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 16,
-		.end_logical_lane = 19,
-		.device_number = PCI_SLOT(NVME_DEVFN),
-		.function_number = PCI_FUNC(NVME_DEVFN),
-		.link_speed_capability = GEN_MAX,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ3,
-	},
+	[DXIO_STORAGE] = { 0 },
+};
+
+static const fsp_dxio_descriptor emmc_descriptor = {
+	.engine_type = PCIE_ENGINE,
+	.port_present = true,
+	.start_logical_lane = 16,
+	.end_logical_lane = 16,
+	.device_number = PCI_SLOT(NVME_DEVFN),
+	.function_number = PCI_FUNC(NVME_DEVFN),
+	.link_speed_capability = GEN_MAX,
+	.turn_off_unused_lanes = true,
+	.clk_req = CLK_REQ3,
+};
+
+static const fsp_dxio_descriptor nvme_descriptor = {
+	.engine_type = PCIE_ENGINE,
+	.port_present = true,
+	.start_logical_lane = 16,
+	.end_logical_lane = 19,
+	.device_number = PCI_SLOT(NVME_DEVFN),
+	.function_number = PCI_FUNC(NVME_DEVFN),
+	.link_speed_capability = GEN_MAX,
+	.turn_off_unused_lanes = true,
+	.clk_req = CLK_REQ3,
 };
 
 static const fsp_ddi_descriptor myst_ddi_descriptors[] = {
@@ -85,6 +101,14 @@ void mainboard_get_dxio_ddi_descriptors(
 		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
 {
+	if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) {
+		printk(BIOS_DEBUG, "Enabling NVMe.\n");
+		myst_dxio_descriptors[DXIO_STORAGE] = nvme_descriptor;
+	} else {
+		printk(BIOS_DEBUG, "Enabling eMMC.\n");
+		myst_dxio_descriptors[DXIO_STORAGE] = emmc_descriptor;
+	}
+
 	*dxio_descs = myst_dxio_descriptors;
 	*dxio_num = ARRAY_SIZE(myst_dxio_descriptors);
 	*ddi_descs = myst_ddi_descriptors;
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
index a3fd355ef1..6446763152 100644
--- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
@@ -12,6 +12,12 @@
 #define SD_DEVFN	PCIE_GPP_2_3_DEVFN
 #define NVME_DEVFN	PCIE_GPP_2_4_DEVFN
 
+enum dxio_port_id {
+	DXIO_WWAN,
+	DXIO_WLAN,
+	DXIO_SD,
+	DXIO_STORAGE
+};
 
 /* This function provides base GPIO configuration table. */
 void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
diff --git a/src/mainboard/google/myst/variants/myst/overridetree.cb b/src/mainboard/google/myst/variants/myst/overridetree.cb
index 989a17ccb9..4433d9ac53 100644
--- a/src/mainboard/google/myst/variants/myst/overridetree.cb
+++ b/src/mainboard/google/myst/variants/myst/overridetree.cb
@@ -26,6 +26,10 @@ fw_config
 		option DISABLED 0
 		option ENABLED 1
 	end
+	field STORAGE 11
+		option EMMC 0
+		option NVME 1
+	end
 end
 
 chip soc/amd/phoenix