soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtk_init_mcu. On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, so it is not necessary to be marked as non-cacheable resource. Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_
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#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_
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#include <symbols.h>
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DECLARE_REGION(dram_dma)
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#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */
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@ -14,6 +14,11 @@
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#define DRAM_INIT_CODE(addr, size) \
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REGION(dram_init_code, addr, size, 4)
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#define DRAM_DMA(addr, size) \
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REGION(dram_dma, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, \
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"DRAM DMA buffer should be multiple of smallest page size (4K)!");
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SECTIONS
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{
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SRAM_START(0x00100000)
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@ -37,7 +42,8 @@ SECTIONS
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SRAM_L2C_END(0x00280000)
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DRAM_START(0x40000000)
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POSTRAM_CBFS_CACHE(0x40000000, 2M)
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DRAM_DMA(0x40000000, 1M)
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POSTRAM_CBFS_CACHE(0x40100000, 1M)
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RAMSTAGE(0x40200000, 256K)
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BL31(0x54600000, 0x60000)
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