t124: nyan: Enable lock bit on pll
A PLL (Phase-Locked Loop) clock must be locked before it is assigned as clock source. Otherwise, this clock is unreliable. Before: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 40009e01, misc(600060e4): 00000000 p base(600060a0): 40002201, misc(600060ac): 00000200 u base(600060c0): 40005001, misc(600060cc): 00000300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 After: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 48009e01, misc(600060e4): 00040000 p base(600060a0): 5801980c, misc(600060ac): 00040800 u base(600060c0): 48005001, misc(600060cc): 00400300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 BUG=None TEST=build nyan and boot Original-Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188447 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 7e8e2854b2b7d1ed20d74891c3d19b6c3dd41c55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ief9efa6937af26fe1a10a7b360fc2f5477416b97 Reviewed-on: http://review.coreboot.org/7414 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Jimmy Zhang
Marc Jones
parent
78a1b8c815
commit
c225e4c335
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@ -97,18 +97,18 @@ struct {
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[OSC_FREQ_OSC12]{
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.khz = 12000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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.pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2},
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.pllp = {.n = 408, .m = 12, .p = 0, .cpcon = 8},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 283, .m = 12, .p = 0, .cpcon = 8}, /* 283 MHz */
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 1, .p = 3}, /* 270 MHz */
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.plld2 = {.n = 95, .m = 1, .p = 1}, /* 570 MHz */
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.plldp = {.n = 90, .m = 1, .p = 3},
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.plld2 = {.n = 95, .m = 1, .p = 1},
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},
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[OSC_FREQ_OSC13]{
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.khz = 13000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0},
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.pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8},
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.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
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.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
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.plld = {.n = 283, .m = 13, .p = 0, .cpcon = 8}, /* 283 MHz*/
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
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@ -132,7 +132,7 @@ struct {
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.plld = {.n = 251, .m = 17, .p = 0, .cpcon = 8}, /* 283.5 MHz */
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.pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 270.75 MHz */
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.plld2 = {.n = 59, .m = 1, .p = 1}, /* 570 MHz */
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.plld2 = {.n = 59, .m = 1, .p = 1}, /* 566.4 MHz */
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},
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[OSC_FREQ_OSC26]{
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.khz = 26000,
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@ -142,7 +142,7 @@ struct {
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.plld = {.n = 283, .m = 26, .p = 0, .cpcon = 8}, /* 283 MHz */
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.pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 2, .p = 3}, /* 266.50 MHz */
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.plld2 = {.n = 88, .m = 2, .p = 1}, /* 570 MHz */
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.plld2 = {.n = 88, .m = 2, .p = 1}, /* 572 MHz */
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},
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[OSC_FREQ_OSC38P4]{
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.khz = 38400,
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@ -170,7 +170,7 @@ struct {
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.plld = {.n = 71, .m = 12, .p = 0, .cpcon = 8}, /* 284 MHz */
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 4, .p = 3}, /* 264 MHz */
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.plld2 = {.n = 95, .m = 4, .p = 1}, /* 570 MHz */
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.plld2 = {.n = 95, .m = 4, .p = 1},
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},
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};
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@ -221,7 +221,7 @@ void sor_clock_start(void)
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setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
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}
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static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock)
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{
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u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT |
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pll.div.m << PLL_BASE_DIVM_SHIFT |
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@ -232,14 +232,16 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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/* Write dividers but BYPASS the PLL while we're messing with it. */
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writel(dividers | PLL_BASE_BYPASS, base);
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/*
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* Set CPCON and LFCON fields (default to 0 if it doesn't exist for
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* this PLL)
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* Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't
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* exist for this PLL)
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*/
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writel(misc_con, misc);
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writel(lock | misc_con, misc);
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/* enable PLL and take it back out of BYPASS (we don't wait for lock
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* because we assume that to be done by the time we start using it). */
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/* Enable PLL and take it back out of BYPASS */
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writel(dividers | PLL_BASE_ENABLE, base);
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/* Wait for lock ready */
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while (!(readl(base) & PLL_BASE_LOCK));
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}
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static void init_utmip_pll(void)
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@ -293,19 +295,16 @@ static void graphics_pll(void)
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*/
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u32 scfg = (1<<28) | (1<<24) | (1<<22);
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writel(scfg, cfg);
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init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp);
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init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc,
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osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE);
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/* leave dither and undoc bits set, release clamp */
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scfg = (1<<28) | (1<<24);
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writel(scfg, cfg);
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/* set lock bit */
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setbits_le32(&clk_rst->plldp_misc, PLLDPD2_MISC_LOCK_ENABLE);
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/* init clock source for disp1 */
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/* init plld (the actual output is plld_out0 that is 1/2 of plld. */
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init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
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setbits_le32(&clk_rst->plld_misc, PLLUD_MISC_LOCK_ENABLE);
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setbits_le32(&clk_rst->plld_misc, PLLD_MISC_CLK_ENABLE);
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udelay(10); /* wait for plld ready */
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/* Init clock source for disp1: plld (actually plld_out0) */
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init_pll(&clk_rst->plld_base, &clk_rst->plld_misc,
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osc_table[osc].plld,
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(PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE));
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}
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/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
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@ -474,11 +473,8 @@ void clock_init(void)
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writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2);
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/* Max out the AVP clock before everything else (need PLLC for that). */
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init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc);
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/* Be more careful with processor clock, wait for the lock. (~10us) */
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setbits_le32(&clk_rst->pllc_misc, PLLC_MISC_LOCK_ENABLE);
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while (!(read32(&clk_rst->pllc_base) & PLL_BASE_LOCK)) /* wait */;
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init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc,
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osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE);
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/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
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* features section in the TRM). */
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@ -517,9 +513,20 @@ void clock_init(void)
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PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
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&clk_rst->pllp_outb);
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init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx);
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init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp);
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init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
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/* init pllx */
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init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
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osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE);
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/* init pllp */
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init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc,
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osc_table[osc].pllp, PLLPAXS_MISC_LOCK_ENABLE);
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/* Set additional bit for pllp: enable override */
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setbits_le32(&clk_rst->pllp_base, PLL_BASE_OVRRIDE);
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/* init pllu */
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init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc,
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osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE);
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init_utmip_pll();
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graphics_pll();
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}
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