GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/cezanne: Increase the FSP_M_SIZE configuration 

On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.

BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.

Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-08-31 12:39:47 -06:00 committed by Karthik Ramasubramanian
parent c35659d930
commit c2310a16ad
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/cezanne/Kconfig
View File

@ -166,7 +166,7 @@ config FSP_M_ADDR
config FSP_M_SIZE config FSP_M_SIZE
hex hex
default 0x80000 default 0xC0000
help help
Sets the size of DRAM allocation for FSP-M in linker script. Sets the size of DRAM allocation for FSP-M in linker script.
@ -179,7 +179,7 @@ config FSP_TEMP_RAM_SIZE
config VERSTAGE_ADDR config VERSTAGE_ADDR
hex hex
depends on VBOOT_SEPARATE_VERSTAGE depends on VBOOT_SEPARATE_VERSTAGE
default 0x2140000 default 0x2180000
help help
Sets the address in DRAM where verstage should be loaded if running Sets the address in DRAM where verstage should be loaded if running
as a separate stage on x86. as a separate stage on x86.