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soc/intel/common/block/smbus: Deduplicate some code 

Reuse existing SMBus code from southbridge/intel/common/smbus_ops.h.

Change-Id: Iea4f6886bb49590f7f96abbfbe631ac9d4dda902
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64432
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2022-05-17 20:29:46 +02:00 committed by Felix Held
parent d8f6d2a92d
commit c2461a174d
3 changed files with 6 additions and 66 deletions
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4
src/soc/intel/common/block/smbus/Kconfig
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@ -1,8 +1,12 @@
config SOC_INTEL_COMMON_BLOCK_SMBUS
bool
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
help
Intel Processor common SMBus support
config FIXED_SMBUS_IO_BASE
default 0xefa0
config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER
bool
default n

66
src/soc/intel/common/block/smbus/smbus.c
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@ -8,61 +8,9 @@
#include <soc/smbus.h>
#include <device/smbus_host.h>
#include <intelblocks/tco.h>
#include <southbridge/intel/common/smbus_ops.h>
#include "smbuslib.h"
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, data);
}
static int lsmbus_read_block(struct device *dev, u8 cmd, u8 bytes, u8 *buffer)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_read(res->base, device, cmd, bytes, buffer);
}
static int lsmbus_write_block(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_write(res->base, device, cmd, bytes, (u8 *)buffer);
}
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
.block_read = lsmbus_read_block,
.block_write = lsmbus_write_block,
};
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
@ -77,18 +25,6 @@ static void pch_smbus_init(struct device *dev)
smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}
static void smbus_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
/*
* `finalize_smbus` function is native implementation of equivalent events
* performed by each FSP NotifyPhase() API invocations.

2
src/soc/intel/common/block/smbus/smbuslib.h
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@ -4,7 +4,7 @@
#define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H
/* SMBus IO Base Address */
#define SMBUS_IO_BASE 0xefa0
#define SMBUS_IO_BASE CONFIG_FIXED_SMBUS_IO_BASE
/* PCI Configuration Space : SMBus */
#define HOSTC 0x40