From c2570dc99800070d987bda05c33113930a506fd6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Apr 2022 13:10:47 +0530 Subject: [PATCH] soc/intel/alderlake: Implement PMC soft strap interface lock This patch performs locking of the PMC soft strap message interface. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC MMIO register 0x104c is set as below. > localhost ~ # iotools mmio_read32 0xfe00104c 0x00000001 Signed-off-by: Subrata Banik Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Eric Lai Reviewed-by: Angel Pons --- src/soc/intel/alderlake/lockdown.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index 5d012d8e1b..f018dbd28d 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -24,8 +24,10 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); - if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); + setbits32(pmcbase + SSML, SSML_SSL_EN); + } } void soc_lockdown_config(int chipset_lockdown)