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src: Update bare access to BOOL CONFIG_ vals to CONFIG() 

BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth 2020-07-24 12:26:21 -06:00 committed by Patrick Georgi
parent f48acbda7b
commit c25c1ebd9e
8 changed files with 15 additions and 15 deletions
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2
src/drivers/spi/tpm/tpm.c
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@ -44,7 +44,7 @@ static struct tpm2_info tpm_info;
* TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of
* debug traces. Right now it is either 0 or 1.
*/
static const int debug_level_ = CONFIG_DEBUG_TPM;
static const int debug_level_ = CONFIG(DEBUG_TPM);
/*
* SPI frame header for TPM transactions is 4 bytes in size, it is described

2
src/soc/intel/apollolake/chip.c
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@ -668,7 +668,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
if (!CONFIG(SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;

6
src/soc/intel/cannonlake/fsp_params.c
View File

@ -374,8 +374,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
@ -448,7 +448,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
#if !CONFIG(SOC_INTEL_COMETLAKE)
params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE;
params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE);
#endif
/* Enable CNVi Wifi if enabled in device tree */

2
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -74,7 +74,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
#endif
if (config->cpu_ratio_override) {

4
src/soc/intel/icelake/fsp_params.c
View File

@ -126,8 +126,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;

4
src/soc/intel/jasperlake/fsp_params.c
View File

@ -103,7 +103,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* Chipset Lockdown */
@ -123,7 +123,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->EndOfPostMessage = EOP_PEI;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = 1;
/* disable Legacy PME */

4
src/soc/intel/skylake/chip.c
View File

@ -223,7 +223,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER;
params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER);
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
@ -328,7 +328,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
params->CpuConfig.Bits.SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];

6
src/soc/intel/tigerlake/fsp_params.c
View File

@ -109,7 +109,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* D3Hot and D3Cold for TCSS */
@ -277,8 +277,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()