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fix some southbridge warnings (trivial) 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-30 21:48:23 +00:00 committed by Stefan Reinauer
parent 495b92b787
commit c269d237f9
4 changed files with 10 additions and 7 deletions
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2
src/southbridge/intel/i82801ax/Kconfig
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@ -20,4 +20,6 @@
config SOUTHBRIDGE_INTEL_I82801AX
bool
select HAVE_HARD_RESET
select USE_WATCHDOG_ON_BOOT

1
src/southbridge/intel/i82801ax/i82801ax_reset.c
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@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <reset.h>
#include <arch/io.h>
void hard_reset(void)

1
src/southbridge/intel/i82801ax/i82801ax_watchdog.c
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@ -22,6 +22,7 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <watchdog.h>
/* TODO: I'm fairly sure the same functionality is provided elsewhere. */

13
src/southbridge/intel/i82870/p64h2_pcibridge.c
View File

@ -8,13 +8,12 @@
static void p64h2_pcix_init(device_t dev)
{
uint32_t dword;
uint16_t word;
uint8_t byte;
u32 dword;
u8 byte;
/* The purpose of changes to HCCR, ACNF, and MTT is to speed up the
PCI bus for cards having high speed transfers. */
/* The purpose of changes to HCCR, ACNF, and MTT is to speed
* up the PCI bus for cards having high speed transfers.
*/
dword = 0xc2040002;
pci_write_config32(dev, HCCR, dword);
dword = 0x0000c3bf;
@ -37,4 +36,4 @@ static const struct pci_driver pcix_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82870_1F0,
};