fix some southbridge warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -20,4 +20,6 @@
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config SOUTHBRIDGE_INTEL_I82801AX
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config SOUTHBRIDGE_INTEL_I82801AX
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bool
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bool
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select HAVE_HARD_RESET
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select USE_WATCHDOG_ON_BOOT
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@ -18,6 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#include <reset.h>
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#include <arch/io.h>
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#include <arch/io.h>
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void hard_reset(void)
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void hard_reset(void)
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@ -22,6 +22,7 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <watchdog.h>
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/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
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/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
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@ -8,13 +8,12 @@
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static void p64h2_pcix_init(device_t dev)
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static void p64h2_pcix_init(device_t dev)
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{
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{
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uint32_t dword;
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u32 dword;
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uint16_t word;
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u8 byte;
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uint8_t byte;
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/* The purpose of changes to HCCR, ACNF, and MTT is to speed
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/* The purpose of changes to HCCR, ACNF, and MTT is to speed up the
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* up the PCI bus for cards having high speed transfers.
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PCI bus for cards having high speed transfers. */
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*/
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dword = 0xc2040002;
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dword = 0xc2040002;
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pci_write_config32(dev, HCCR, dword);
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pci_write_config32(dev, HCCR, dword);
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dword = 0x0000c3bf;
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dword = 0x0000c3bf;
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@ -37,4 +36,4 @@ static const struct pci_driver pcix_driver __pci_driver = {
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.vendor = PCI_VENDOR_ID_INTEL,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82870_1F0,
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.device = PCI_DEVICE_ID_INTEL_82870_1F0,
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};
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};
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