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siemens/mc_apl4: Disable CLKREQ of PCIe root ports 

All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".

Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2018-11-09 08:54:35 +01:00 committed by Werner Zeh
parent 4946804f0b
commit c27ce827dc
1 changed files with 6 additions and 5 deletions
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11
src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
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@ -6,11 +6,12 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
# Disable all clkreq of PCIe root ports as SMARC interface do not
# have this pins.
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"