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binaryPI: Drop remains of ACPI S3 on FCH 

Never reached and actual code was already wiped out.

Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20623
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-07-16 04:47:23 +03:00
parent a61884a8a1
commit c27daff542
5 changed files with 0 additions and 53 deletions
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2
src/cpu/amd/pi/Makefile.inc
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@ -17,8 +17,6 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
ramstage-$(CONFIG_SPI_FLASH) += spi.c
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
romstage-y += romstage.c

42
src/cpu/amd/pi/spi.c
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@ -1,42 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <spi-generic.h>
#include <spi_flash.h>
#include "s3_resume.h"
void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
{
struct spi_flash flash;
spi_init();
if (spi_flash_probe(0, 0, &flash)) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
/* Dont make flow stop. */
return;
}
spi_flash_volatile_group_begin(&flash);
spi_flash_erase(&flash, pos, size);
spi_flash_write(&flash, pos, sizeof(len), &len);
spi_flash_write(&flash, pos + sizeof(len), len, buf);
spi_flash_volatile_group_end(&flash);
return;
}

3
src/northbridge/amd/pi/00630F01/northbridge.c
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@ -629,9 +629,6 @@ static void domain_read_resources(device_t dev)
static void domain_enable_resources(device_t dev)
{
if (acpi_is_wakeup_s3())
agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */

3
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -634,9 +634,6 @@ static void domain_read_resources(device_t dev)
static void domain_enable_resources(device_t dev)
{
if (acpi_is_wakeup_s3())
AGESAWRAPPER(fchs3laterestore);
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3())
AGESAWRAPPER(amdinitmid);

3
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -648,9 +648,6 @@ static void domain_read_resources(device_t dev)
static void domain_enable_resources(device_t dev)
{
if (acpi_is_wakeup_s3())
AGESAWRAPPER(fchs3laterestore);
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3())
AGESAWRAPPER(amdinitmid);