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pcengines/apu2: Refactor reading memory strap 

Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-01-16 19:58:53 +02:00
parent 0a06205ec6
commit c27df87878
3 changed files with 18 additions and 10 deletions
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13
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -22,6 +22,7 @@
#include "heapManager.h" #include "heapManager.h"
#include "FchPlatform.h" #include "FchPlatform.h"
#include "cbfs.h" #include "cbfs.h"
#include "gpio_ftns.h"
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#include "imc.h" #include "imc.h"
#endif #endif
@ -125,13 +126,12 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
return AGESA_SUCCESS; return AGESA_SUCCESS;
} }
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
AGESA_STATUS Status = AGESA_UNSUPPORTED; AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
int index = 0; u8 index = get_spd_offset();
if (info->MemChannelId > 0) if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
@ -140,14 +140,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf
if (info->DimmId != 0) if (info->DimmId != 0)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
/* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/ /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
printk(BIOS_INFO, "Reading SPD index %d\n", index);
if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
die("No SPD data\n"); die("No SPD data\n");

14
src/mainboard/pcengines/apu2/gpio_ftns.c
View File

@ -16,6 +16,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/cimx_util.h>
#include "FchPlatform.h"
#include "gpio_ftns.h" #include "gpio_ftns.h"
void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
@ -32,3 +33,16 @@ void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio,
bdata |= setting; /* set direction and data value */ bdata |= setting; /* set direction and data value */
*memptr = bdata; *memptr = bdata;
} }
int get_spd_offset(void)
{
u8 index = 0;
/* One SPD file contains all 4 options, determine which index to
* read here, then call into the standard routines.
*/
u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
return index;
}

1
src/mainboard/pcengines/apu2/gpio_ftns.h
View File

@ -17,6 +17,7 @@
#define GPIO_FTNS_H #define GPIO_FTNS_H
void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
int get_spd_offset(void);
#define IOMUX_OFFSET 0xD00 #define IOMUX_OFFSET 0xD00
#define GPIO_OFFSET 0x1500 #define GPIO_OFFSET 0x1500