google/reef: Enable I2C TPM
Enable the I2C based TPM on the reef board at bus 2 and address 0x50. This makes vboot functional without needing MOCK_TPM and results in the following in the SSDT: Device (TPMI) { Name (_HID, "GOOG0005") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "I2C TPM") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) { 0x00000039 } }) } Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16398 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -7,8 +7,10 @@ config BOARD_GOOGLE_BASEBOARD_REEF
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select I2C_TPM
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select TPM2
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if BOARD_GOOGLE_BASEBOARD_REEF
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@ -16,6 +18,12 @@ config BASEBOARD_REEF_LAPTOP
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def_bool n
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select SYSTEM_TYPE_LAPTOP
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config DRIVER_TPM_I2C_BUS
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hex "0x2"
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config DRIVER_TPM_I2C_ADDR
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hex "0x50"
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config CHROMEOS
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select LID_SWITCH if BASEBOARD_REEF_LAPTOP
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@ -99,7 +99,13 @@ chip soc/intel/apollolake
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end
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end
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.2 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
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device i2c 50 on end
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end
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end # - I2C 2
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device pci 16.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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