mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes

Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/scaleway/tagada/gpio_defs.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_GPIO_DEFS_H
+#define _MAINBOARD_GPIO_DEFS_H
+
+#include <soc/gpio_defs.h>
+
+// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED
+#define GPIO_GPIO_0				0
+#define R_PAD_CFG_DW0_GPIO_0			0x4d8
+#define PID_GPIO_0				PID_NorthCommunity
+
+// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn
+#define GPIO_GPIO_4				4
+#define R_PAD_CFG_DW0_GPIO_4			0x568
+#define PID_GPIO_4				PID_SouthCommunity
+
+// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn
+#define GPIO_GPIO_5				5
+#define R_PAD_CFG_DW0_GPIO_5			0x570
+#define PID_GPIO_5				PID_SouthCommunity
+
+
+// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select
+#define GPIO_GPIO_8				8
+#define R_PAD_CFG_DW0_GPIO_8			0x5c8
+#define PID_GPIO_8				PID_SouthCommunity
+
+// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose
+#define GPIO_GPIO_9				9
+#define R_PAD_CFG_DW0_GPIO_9			0x5d0
+#define PID_GPIO_9				PID_SouthCommunity
+
+#endif /* _MAINBOARD_GPIO_DEFS_H */

src/mainboard/scaleway/tagada/hsio.c

@@ -1,12 +1,62 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/mmio.h>
+#include <console/console.h>
 #include <hsio.h>
+#include <gpio_defs.h>
 #include <soc/fiamux.h>
 
+#ifdef __RAMSTAGE__
+static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config)
+{
+	uint32_t reg32;
+	bool m2a_pcie, m2b_pcie;
+	uint8_t entry;
+
+	/* Detects modules type */
+	// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
+	reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4, R_PAD_CFG_DW0_GPIO_4));
+	m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0;
+	// _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
+	reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5, R_PAD_CFG_DW0_GPIO_5));
+	m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0;
+
+	printk(BIOS_DEBUG,
+	       "GPIO values from M2 slots A:%d B:%d "
+	       "(0=SATA, 1=PCIe or not populated)\n",
+	       m2a_pcie, m2b_pcie);
+
+	// HSIO default config is for PCIe, only update for SATA
+	// (also secondary PCIe lines are already set depending on SKU)
+	for (entry = 0; entry < num_of_entry; entry++) {
+		BL_ME_FIA_MUX_CONFIG *mux_config = &(config[entry].FiaConfig.MuxConfiguration);
+		BL_ME_FIA_SATA_CONFIG *sata_config =
+			&(config[entry].FiaConfig.SataLaneConfiguration);
+		if (!m2a_pcie) {
+			// change Lane 14 config
+			mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel =
+				BL_ME_FIA_MUX_LANE_SATA;
+			sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel =
+				BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
+		}
+		if (!m2b_pcie) {
+			// change Lane 12 config
+			mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel =
+				BL_ME_FIA_MUX_LANE_SATA;
+			sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =
+				BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
+		}
+	}
+}
+#endif
+
 size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
 {
-    size_t num;
-    num = ARRAY_SIZE(tagada_hsio_config);
-    (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
-    return num;
+	size_t num;
+	num = ARRAY_SIZE(tagada_hsio_config);
+#ifdef __RAMSTAGE__
+	update_hsio_info_for_m2_slots(num, tagada_hsio_config);
+#endif
+	(*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
+	return num;
 }

src/mainboard/scaleway/tagada/hsio.h

@@ -6,7 +6,7 @@
 #include <fsp/util.h>
 
 #ifndef __ACPI__
-const BL_HSIO_INFORMATION tagada_hsio_config[] = {
+DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = {
 	/*
 	 * Supported Lanes:
 	 *    20