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mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot 

Keep the clock source for PCIe slots as always on. Also turn off the
unused (0/1/5/6) clock sources. Currently bilby only uses clock sources
2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe
external slot. And clock source 2 is routed for M.2 PCIe slot.

TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2021-04-15 14:56:03 +05:30 committed by Nick Vaccaro
parent 0e5b713d32
commit c29df438c4
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/amd/bilby/devicetree.cb
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@ -137,13 +137,13 @@ chip soc/amd/picasso
}"
# genral purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_REQ"
register "gpp_clk_config[1]" = "GPP_CLK_REQ"
register "gpp_clk_config[0]" = "GPP_CLK_OFF"
register "gpp_clk_config[1]" = "GPP_CLK_OFF"
register "gpp_clk_config[2]" = "GPP_CLK_REQ"
register "gpp_clk_config[3]" = "GPP_CLK_REQ"
register "gpp_clk_config[4]" = "GPP_CLK_REQ"
register "gpp_clk_config[5]" = "GPP_CLK_REQ"
register "gpp_clk_config[6]" = "GPP_CLK_REQ"
register "gpp_clk_config[3]" = "GPP_CLK_ON"
register "gpp_clk_config[4]" = "GPP_CLK_ON"
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_BALANCED"