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rockchip: rk3288: correct ddr 300MHz clock setting 

CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
setting can't meet this request, so modify it

BRANCH=None
BUG=None
TEST=Set ddr frequency to 300MHz and boot from mickey

Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5
Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282445
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
huang lin 2015-06-30 10:01:14 +08:00 committed by Patrick Georgi
parent a1e5a7761a
commit c2b48e55f1
1 changed files with 1 additions and 1 deletions
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2
src/soc/rockchip/rk3288/clock.c
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@ -360,7 +360,7 @@ void rkclk_configure_ddr(unsigned int hz)
switch (hz) {
case 300*MHz:
dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1};
dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2};
break;
case 533*MHz: /* actually 533.3P MHz */
dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};