diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 8e1d212363..072dad67f8 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -39,6 +39,7 @@
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "northbridge/intel/i3100/i3100.h"
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@@ -54,10 +55,6 @@
 #define SATA_MODE_IDE  0x00
 #define SATA_MODE_AHCI 0x01
 
-/* RCBA registers */
-#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
-
 #define RCBA_RPC   0x0224 /* 32 bit */
 
 #define RCBA_TCTL  0x3000 /*  8 bit */
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 8aae1a9aed..9fb2996edb 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -64,6 +64,8 @@
 #define DRC_NOECC_MODE        (0 << 20)
 #define DRC_72BIT_ECC         (1 << 20)
 
+#define RCBA 0xF0
+#define DEFAULT_RCBA 0xFEA00000
 
 #ifdef __GNUC__
 int bios_reset_detected(void);