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{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() 

Use hexdump() instead of dump_mem().

Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS 2018-11-27 09:31:27 +01:00 committed by Kyösti Mälkki
parent 15b83da39a
commit c2c1dc9c76
20 changed files with 0 additions and 63 deletions
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2
src/mainboard/amd/mahogany_fam10/romstage.c
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@ -100,8 +100,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -100,8 +100,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -101,8 +101,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -104,8 +104,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
printk(BIOS_DEBUG, "\n");
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -96,8 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_disable_reboot(GPIO_DEV);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -96,8 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_disable_reboot(GPIO_DEV);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -98,8 +98,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -103,8 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

2
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -110,8 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);

13
src/northbridge/amd/amdfam10/debug.c
View File

@ -299,19 +299,6 @@ void dump_io_resources(u32 port)
}
}
void dump_mem(u32 start, u32 end)
{
u32 i;
printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
printk(BIOS_DEBUG, "\n");
}
#if IS_ENABLED(CONFIG_DIMM_DDR2)
void print_tx(const char *strval, u32 val)
{

1
src/northbridge/amd/amdfam10/debug.h
View File

@ -38,7 +38,6 @@ void dump_smbus_registers(void);
#endif
void dump_io_resources(u32 port);
void dump_mem(u32 start, u32 end);
void print_tx(const char *strval, u32 val);
void print_t(const char *strval);

12
src/northbridge/intel/e7505/debug.c
View File

@ -183,15 +183,3 @@ void dump_io_resources(unsigned port)
port++;
}
}
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
printk(BIOS_DEBUG, "\n");
}

1
src/northbridge/intel/e7505/debug.h
View File

@ -22,6 +22,5 @@ void dump_pci_devices_on_bus(unsigned busn);
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
void dump_io_resources(unsigned port);
void dump_mem(unsigned start, unsigned end);
#endif

1
src/northbridge/intel/fsp_rangeley/northbridge.h
View File

@ -69,7 +69,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#ifndef __SIMPLE_DEVICE__

1
src/northbridge/intel/haswell/haswell.h
View File

@ -228,7 +228,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */

12
src/northbridge/intel/i945/debug.c
View File

@ -96,15 +96,3 @@ void dump_spd_registers(void)
printk(BIOS_DEBUG, "\n");
}
}
void dump_mem(unsigned int start, unsigned int end)
{
unsigned int i;
printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
printk(BIOS_DEBUG, "\n");
}

1
src/northbridge/intel/i945/i945.h
View File

@ -379,7 +379,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned int dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned int start, unsigned int end);
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);

1
src/northbridge/intel/nehalem/nehalem.h
View File

@ -277,7 +277,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */

1
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -219,7 +219,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
#endif /* !__SMM__ */

1
src/soc/intel/fsp_baytrail/include/soc/baytrail.h
View File

@ -63,7 +63,6 @@ void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* __PRE_RAM__ */