GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/mainboard: remove MMIO macros 

This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.

Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Idwer Vollering 2020-01-05 01:44:25 +01:00 committed by Kyösti Mälkki
parent 7c07110923
commit c2ce370f30
8 changed files with 43 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/amd/thatcher/romstage.c
View File

@ -18,6 +18,7 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <superio/smsc/lpc47n217/lpc47n217.h>
@ -50,5 +51,5 @@ void board_BeforeAgesa(struct sysinfo *cb)
outb(0x1, 0xcd7);
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
*(u8 *)0xfed80101 = 0x98;
gpio_100_write8(0x1, 0x98);
}

17
src/mainboard/asrock/imb-a180/bootblock.c
View File

@ -21,23 +21,20 @@
void bootblock_mainboard_early_init(void)
{
volatile u32 *addr32;
u32 t32;
u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
t32 &= 0xfff8ffff;
*addr32 = t32;
reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
t32 &= 0xffffbffb;
*addr32 = t32;
reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
misc_write32(0x40, reg32);
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

8
src/mainboard/asus/am1i-a/bootblock.c
View File

@ -113,18 +113,16 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void)
{
volatile u32 i, val, *addr32;
volatile u32 i, val;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Configure ClkDrvStr1 settings */
addr32 = (u32 *)0xfed80e24;
*addr32 = 0x030800aa;
misc_write32(0x24, 0x030800aa);
/* Configure MiscClkCntl1 settings */
addr32 = (u32 *)0xfed80e40;
*addr32 = 0x000c4050;
misc_write32(0x40, 0x000c4050);
/* Configure SIO as made under vendor BIOS */
ite_gpio_conf(GPIO_DEV);

12
src/mainboard/asus/f2a85-m/bootblock.c
View File

@ -16,27 +16,25 @@
#include <bootblock_common.h>
#include <device/pnp_type.h>
#include <southbridge/amd/common/amd_defs.h>
#include <amdblocks/acpimmio.h>
#include <stdint.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
u32 reg32;
reg32 = SB_MMIO_MISC32(0x28);
reg32 = misc_read32(0x28);
reg32 &= 0xffc7ffff;
reg32 |= 0x00100000;
SB_MMIO_MISC32(0x28) = reg32;
misc_write32(0x28, reg32);
reg32 = SB_MMIO_MISC32(0x40);
reg32 = misc_read32(0x40);
reg32 &= ~0x80u;
SB_MMIO_MISC32(0x40) = reg32;
misc_write32(0x40, reg32);
}
static void superio_init_m(void)

12
src/mainboard/biostar/a68n_5200/romstage.c
View File

@ -21,12 +21,10 @@
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <amdblocks/acpimmio.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)
@ -36,14 +34,14 @@ static void sbxxx_enable_48mhzout(void)
/* most likely programming to 48MHz out signal */
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
u32 reg32;
reg32 = SB_MMIO_MISC32(0x28);
reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
SB_MMIO_MISC32(0x28) = reg32;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
reg32 = SB_MMIO_MISC32(0x40);
reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
SB_MMIO_MISC32(0x40) = reg32;
misc_write32(0x40, reg32);
}
void board_BeforeAgesa(struct sysinfo *cb)

17
src/mainboard/biostar/am1ml/bootblock.c
View File

@ -61,23 +61,20 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void)
{
volatile u32 *addr32;
u32 t32;
u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
t32 &= 0xfff8ffff;
*addr32 = t32;
reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
t32 &= 0xffffbffb;
*addr32 = t32;
reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
misc_write32(0x49, reg32);
/* Configure SIO as made under vendor BIOS */
ite_evc_conf(ENVC_DEV);

20
src/mainboard/hp/abm/romstage.c
View File

@ -18,6 +18,7 @@
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <amdblocks/acpimmio.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
@ -25,8 +26,7 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
u32 *addr32;
u32 t32;
u32 reg32;
/* For serial port option, plug-in card on LPC. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@ -47,17 +47,15 @@ void board_BeforeAgesa(struct sysinfo *cb)
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
t32 |= 0x00010000; // Set bit 16 for 25MHz
*addr32 = t32;
reg32 = misc_read32(0x28);
reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
reg32 |= 0x00010000; // Set bit 16 for 25MHz
misc_write32(0x28, reg32);
/* Enable Auxiliary OSCOUT1/OSCOUT2 */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
t32 &= 0xffffff7b; // clear 2, 7
*addr32 = t32;
reg32 = misc_read32(0x40;
reg32 &= 0xffffff7b; // clear 2, 7
misc_write32(0x40, reg32);
nct5104d_enable_uartd(SERIAL_DEV);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

12
src/mainboard/msi/ms7721/bootblock.c
View File

@ -19,12 +19,10 @@
#include <device/pnp_ops.h>
#include <device/pnp_type.h>
#include <stdint.h>
#include <southbridge/amd/common/amd_defs.h>
#include <amdblocks/acpimmio.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SUPERIO_ADDRESS 0x4e
@ -76,14 +74,14 @@ static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
u32 reg32;
reg32 = SB_MMIO_MISC32(0x28);
reg32 = misc_read32(0x28);
reg32 &= 0xffc7ffff;
reg32 |= 0x00100000;
SB_MMIO_MISC32(0x28) = reg32;
misc_write32(0x28, reg32);
reg32 = SB_MMIO_MISC32(0x40);
reg32 = misc_read32(0x40);
reg32 &= ~0x80u;
SB_MMIO_MISC32(0x40) = reg32;
misc_write32(0x40, reg32);
}
void bootblock_mainboard_early_init(void)